Harish M

Leading IP/Subsystem verification (SV UVM) and RTL development for mutliple IPs, Subsystems : 1.) Debug Subsystem for a multi core architecture. 2.) Processor subsystem. 3.) Multiple serial IPs I2s, USB, MMC/SD/SDIO, SPI etc 4.) RTL development for multiple IPs. 5.) Hibernate Low power subsystem. 6.) Analog subsystem 7.) I2c, UART, EEProm, Flash controller, Hibernate subsystem, Keyscan, PS2, LED controller. Leading a 10 member contractor team for the Soc verification of Cortex based MCU. SOC level verification of multiple modules and use case testcases mostly in C and verilog (modules like GPIO, I2C, UART, SSI, CPF based Low Power Modes, Flash Memory Controller, Eeprom,watch dog timer, Hibernate Low Power module,keyscan,ledsequencer,ps2). Flow setup for postlayout, Mixed signal simulation and Designware based Axi/Ahb Post silicon validation of power gated and non - powergated low power modes, GPIOs, Clock system, Reset controller. Formal verification of Minmuxing logic using cadence IFV Specialties: C based Soc verification for Arm based platforms - Across 7 platforms System verilog OVM/UVM based IP verification - CPF based low power mode verification AHB/AXI protocol knowledge Slicon validation - Across 2 platforms Formal verification using IFV - Across multiple SoCs and IPs CPF based low power mode simulations Leading IP RTL development. Leading IP and Subsystem Verification.