Vijeth Jayaswamy

• Developed the assertions to verify the clock scaling and gating at the bus master interface when no traffic. • Involved in root causing the bug which delayed the clock scaling by hundreds of cycles in the DCD (Dynamic Clock Division) feature implemented at SoC level for Qualcomm’s AI chip. • Worked on modifications to the chip level SV/UVM Environment to verify AHB, AXI, QSBAXI buses. • Developed and debugged the SoC integration level tests to verify the NOC bus timeout feature and fault trigger. • Assisting the DDR team for post-silicon vector development and debug to verify the step size of Clock delay circuit (CDC).

• Analyzed and implemented the Procurement and Financial modules in ERP Cloud at SunCoke Energy and Pittsburg State University in collaboration with Functional Consultants. • Coordinated the interaction between clients and consultants for the customization of the product offerings.

During the period, worked on the project 'Wireless Data Transmission with Energy Harvesting for Gas Turbines' under the guidance of A N Vishwanath Rao (Scientist G) and Vasanta Lakshmi (Scientist E).

Selected as the undergraduate intern to work under Prof. S R Mahadeva Prasanna. The project 'GUI for Speech Analysis' was built from ground up during the period.