Vijayeendra Rao

Vijayeendra Rao

TPU Silicon Validation Engineer @ Google

About

Highly motivated and results-oriented Senior ASIC Test Engineer experienced in designing, developing, and executing test plans for complex ASIC products. Proven ability to bring up ASICs, perform functional and performance validation, and debug failures. Expertise in Python scripting for test automation, data analysis, and instrument control. Adept at collaborating with cross-functional teams, including design, verification, and software engineers, to ensure comprehensive test coverage and successful product delivery. Passionate about contributing to cutting-edge hardware development. Programming Languages: Python, MATLAB, VB.net, C, C++, Verilog, SystemVerilog ASIC Testing: Bring-up, Validation, Debugging, Test Plan Development, Functional Testing, Performance Testing, Characterization Test Automation: Scripting, Instrument Control, Data Analysis, Report Generation Lab Instruments: Oscilloscope, Multimeter, AWG, Power supply, Temperature Controller, Spectrum Analyzer, Logic Analyzer. PCB Design: Cadence Capture CIS, PCB Editor

Country

United States

City

Sunnyvale

Industry

Electrical & Electronic Manufacturing

Skill

Printed Circuit Board (PCB) Design, Python, C (Programming Language), C++, VHDL, Synopsys tools, Cadence

Experience

Google

TPU Silicon Validation Engineer

Google

LinkedIn
2025-5 - Present · 1 yr 5 mos

Sunnyvale, California, United States

Infinera

Senior Hardware Engineer

Infinera

LinkedIn
2022-9 - 2025-5 · 2 yrs 9 mos

Sunnyvale, California, United States

• Spearheaded the design of comprehensive test plans for High Resolution Data Converters, focusing on characterizing critical performance parameters such as Linearity, Noise, DNL, and INL. • Developed and maintained Python-based test routines to rigorously characterize parts for both functionality and performance significantly improving testing efficiency. • Collaborated closely with design engineers to analyze test results, identify areas for improvement, and drive design enhancements. • Contributed to the digital design verification of the SPI protocol, ensuring robust and reliable communication. • Automated lab instruments for data capture and analysis using Python, streamlining the testing process and improving data accuracy. • Developed firmware for FPGA/Arduino using C++, expanding testing capabilities and enabling custom test solutions. • Designed PCB schematics and layouts for ASIC evaluation boards using Cadence Capture CIS and PCB Editor 17.4, facilitating rapid prototyping and evaluation.

Infinera

Hardware Development Engineer 2

Infinera

LinkedIn
2021-9 - 2022-9 · 1 yr 1 mo

Sunnyvale, California, United States

Saaz Micro Inc.

Imaging IC & System Design Engineer

Saaz Micro Inc.

LinkedIn
2018-8 - 2021-9 · 3 yrs 2 mos

Thousand Oaks, California, United States

• Successfully delivered an Automated Test system using Python to qualify IR Camera product which included writing scripts for capturing frames from FPA controlled by ASIC/FPGA which was followed by image processing modules to report quality standards like QE, Responsivity, Operability, and other parameters. • Automated report generation of production camera and graphical analysis of test results. • Expertise in Python for automating the communication of different Lab instruments including but not limited to Thermal Chamber, Blackbody, Function generator, Temperature controller and other test systems. • Experience working with embedded system design and knowledge of UART, Serial, SPI communication protocols. • Designed a Python based GUI for end-to-end testing of an in-house camera involving Image analysis routines like Histogram analysis and programming frame grabbers for image acquisition.

Saaz Micro Inc.

Digital Design Engineer

Saaz Micro Inc.

LinkedIn
2018-8 - 2019-7 · 1 yr

Greater Los Angeles Area

Education

The University of Texas at Dallas

The University of Texas at Dallas

LinkedIn

Electrical, Electronics and Communications Engineering

2016 - 2018 · 2 yrs
Sri Jayachamarajendra College Of Engineering

Sri Jayachamarajendra College Of Engineering

LinkedIn

Instrumentation Technology and Engineering

2012 - 2016 · 4 yrs

Vijayeendra Rao's Contact Information

Email

******@***.com

Phone

(**) *** ****

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