Naveen M J
DFT Engineer II @ Mirafra Technologies
About
3+ years of experience in DFT - ATPG, Scan
India
Bengaluru
Information Technology & Services
Gate Level Simulation, Semiconductor Industry, Semiconductor Engineering, Scan Insertion, TCL, Bash, Digital Electronics, Computer Architecture, Electrical Machines, Business Data Management, Business Analysis, Python (Programming Language), computational thinking, Embedded Systems, Embedded Software, Embedded Software Programming, Embedded C, Power Electronics, Electric Motors, Motor Control
Experience
DFT Engineer II
Mirafra Technologies
Bengaluru
VLSI DFT Engineer - L2
Wipro
Bengaluru, Karnataka, India
1. SiLabs Account (2022 to 2023): Worked on DFT ATPG and GLS for automotive based SoC. 2. Google Account (2023 to 2024): Worked on DFT Scan insertion, Wrapper analysis, EDT compression analysis, ATPG (Stuck-at, Transition and advanced static bridging and open fault model), GLS (power aware and non-power aware), ICL network connectivity simulation.
Intern
Navtat Solutions OPC Pvt. Ltd.
Bengaluru, Karnataka, India
Research Intern
InsightED Education Solutions
http://www.ikasle.in
Education
PSG College of Technology
Electrical and Electronics Engineering
Indian Institute of Technology, Madras
Data Science and Applications
Naveen M J's Contact Information
Phone
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