Teodoro Mastellone
FPGA v&v engineer @ Capgemini Engineering
Italy
Tivoli
Defense & Space
Electronic Engineering, Verilog, VHDL, Progettazione circuiti stampati, LabVIEW, Matlab, C
Experience
FPGA v&v engineer
Capgemini Engineering
Pomezia, Latium, Italy
FPGA v&v engineer
Capgemini Engineering
Rome, Latium, Italy
Sviluppatore firmware C/VHDL
aizoOn Technology Consulting
Rome, Latium, Italy
Sviluppatore per sistemi embedded
T&T
Napoli
Neapolis Innovation Summer Campus 2021
STMicroelectronics
Arzano
Education
Università degli Studi di Napoli Federico II
Università degli Studi di Napoli Federico II
Teodoro Mastellone's Contact Information
Phone
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