steve sweet

Managed external ASIC design teams developing precision analog, memories, and mixed-signal military spec IC's.

Coordinated and participated in design, layout and verification of four active ASIC designs. ➢ Worked closely with customers to develop innovative system level architectures that maximize performance with our mixed-signal ASIC designs. Circuit designed and implemented on silicon: ➢ RFID implantable glucose monitor ASIC: field powered design, 13.56MHz clock/data recovery adhering to ISO-15693, internal photodiodes and related signal processing, EEPROM with internal charge pump, low power reference, 10-bit ADC. Use of thick oxide and extended drain devices in a high voltage regulator (6-18V input). ➢ MEMS control ASIC: strain gauge sensing and related signal processing, ADC, EEPROM, charge pump, reference, oscillator & PLL. ➢ Blood Oximeter LED Driver ASIC: low noise 2uVrms (0.1Hz to 16Hz) 12-bit, 16 channel DAC

➢ Led design/layout/verification team of 10 people working on 15 active analog/mixed signal designs with revenue of $25M/yr. ➢ Dual role as Lead designer bringing 3 products from design conception to full production. ➢ Overhauled and systematized the design review and verification procedure to minimize ASIC rev. changes. ➢ part time role as System Architect/FAE for the group, providing system level solutions for potential customers. Relevant circuits designed and implemented on silicon: ➢ Defibrillator/Pacemaker ASIC: subthreshold design of ECG amplifier, reference, oscillator. Design using 40V tolerant NMOS, PMOS high voltage devices. High efficiency boost converter. ➢ Implantable glucose monitor: 16 bit sigma delta ADC, low leakage (<4pA max) input for potentiostat sensing. Other experience: ➢ Tools: Cadence & Orcad for design/simulation, Synopsis & Cadence for verification, ICEditors for layout.

➢ Lead designer 5+ designs from concept to full production ➢ Collaborated with potential customers to develop ASIC system architecture solutions, resulting in 10+ design wins over 2 years. Relevant circuits designed and implemented on silicon: ➢ Automotive capacitive fluid level sensor ASIC: Enhanced latchup immunity design, capacitive sensor. ➢ Battery powered glassbreak detector: subthreshold design of rail-rail fetless microphone amplifier, bandgap reference, internal RC-oscillator, peak detectors, lowpass & bandpass filters. ➢ Extensive design familiarity with sigma-delta and successive approximation ADCs, R-C & crystal oscillators, numerous op-amp and comparator design topologies. Other experience: ➢ Performed layout, LVS/DRC verification and bench testing for most designs worked on during this period. ➢ Mead course in Advanced Analog CMOS IC Design (2001).

➢ Assisted in design of 8+ ASICs from concept to full production. Relevant circuit design experience: ➢ low power/subthreshold design: crystal oscillator circuit <1uA, advanced duty-cycling of critical analog blocks. ➢ SCF, sampled data systems used to implement filters, gain stages, reference voltages and oscillators in various ASICS. Other experience: ➢ Developed a part library and netlist procedure for Orcad schematic capture. ➢ Performed layout, LVS/DRC verification and bench testing for most designs worked on during this period

Developed production test platforms for both wafer sort and final test for 4 ASICs. ➢ Streamlined numerous existing test programs to reduce test time and improve yield. ➢ Worked closely with customers to implement desired test performance.