Anurag Agrawal

As Chief Architect of Tofino Switching silicon, I am leading end-to-end innovation and influencing every aspect of silicon development from concept to tapeout to quality production - Leading silicon architecture of multi-generations of P4 and PISA programmable multi-terabit ethernet networking switches (6.4T-6.5T Tofino, 12.8T-12.9T Tofino2, 25.6T-25.7T Tofino3, ...) - Driving strategic roadmap decisions and customer interactions - Facilitating Build vs Buy, IP vendor selections, technology selection and tradeoffs - Leading pathfinding from concept to approval to unlock new product opportunities - Driving alignment across large organization for product specifications, features & PRD - Strong leadership and interpersonal skills, collaborative team builder, mentor Experience and Expertise: - ASIC development from concept to production silicon with several first pass silicon successes - System, SW and Compiler codesign - Advanced process nodes (TSMC 130nm - 3nm) - Yield & product costs, PPA optimizations - Advanced 2.5D/3D packaging (CoWoS, EMIB) - HSIO (28G NRZ … 224G PAM4), >16GHz Die2Die/UCIe, Bunch-of-wires BoW, - High speed ethernet ports e.g. 50G/100G/400G/800G/1600G - Cu and Optical module (Passive/Active), Co-packaged optics, silicon photonics integration - Scale-out / Scale-up and Clos topologies, Distributed Compute/Memory/Storage architectures - HPC, AI & ML In-network collectives acceleration

Continued the work of - Barefoot Networks silicon architecture stewardship and innovations - Bringing technical leadership voice to executive team for strategic tradeoffs - Customer and industry trends - Culture ambassador and coach

Extensive experience in semiconductor, frontend ASIC development processes including architecture and design of several networking chips. Experienced in advanced packaging technologies, COT flow and making right tradeoffs for better PPA. Currently Managing, Leading and Defining Barefoot's Legendry Switch ASIC architectures - Current and Future Generations. - Architected the Traffic Manager (TM) with truly Shared data buffer for Tofino2 (12.9Tbps) and Tofino (6.5Tbps) Switch ASICs - Also managed Tofino TM Design, DV and PD teams for successful delivery of TM and Packet Buffer Tofino is TSMC 16nm technology ASIC, working well in customer hands and racking rave reviews everywhere. The Tofino2 is further advance node ASIC with chiplet and advance packaging technologies. Architected the chip to chip link definition and managed/involved the whole development of chiplet and related things. With my startup experiences, can do attitude and drive to learn continuously, I am confident to impact very positively to any ASIC team.

• Responsible for leading multiple architects/micro-architects on TF (Fabric chip, 2x cores of 64x10G each) chip, foresaw an opportunity to reduce a network-tier and improve system scalability, providing big cost/power benefit to customers through a novel arch pivot to make TF work as a single 128x10G.  Developed a simulation model and ran hundreds of scenarios/traffic patterns over two months to guarantee arch. robustness and advantages. Presented to execs. and CTO, resulting in the coveted STAR award recognition, high priority patent, and PoR for next- gen fabric chips. • Led and contributed to variety of silicon (all four in production platforms—MX, QFX) from concept to implementation using TSMC 65-28nm and IBM 90-32nm processes, covering: 250K queues’ HQoS, Chip-to-chip links, high-BW buffers, caches w/atomics, packet parsers & rewrites, etc.

Joined at the early stage of the startup as 11th employee. - Rose to lead complete frontend design work within couple of years from a design engineer role - Handled multiple tasks related to front end ASIC development activity including microarchitecture, RTL, Synthesis and interfaced with DV and physical design teams. - Worked closely with architects and custome circuit teams for best product performance ASIC Solution: Industry's First at the time as 36 ports x 10Gbps high perfomance ethernet shared-memory switching datapath solution in TSMC 90nm process. Architecture and designs made into the Cisco's Cat5K products post acquisition.

Worked on ethernet switch fabric related asic architecture for Hybrid Memory solution enabling onchip + offchip memory for data buffer and queuing. Project Capilano (44G).

Worked on IP core development for various ASICs.

Firmware developer for electronic cameras and printers