Saket Kumar

Physical Design engineer with 20+ years of experience delivering high-performance CPU, GPU and networking ASICs across advanced technology nodes from 32nm to 2nm. Extensive hands-on expertise across the complete RTL-to-GDS implementation flow, including floorplanning, power grid architecture, placement optimization, clock tree synthesis, MCMM timing closure, EM/IR analysis and physical signoff. Contributed to 15+ successful silicon tapeouts, with ownership spanning CPU cores, GPU subsystems and large SoC blocks. Strong focus on PPA optimization (performance, power and area) through floorplan architecture, congestion mitigation, power grid planning and timing convergence. Experienced in early design feasibility analysis and implementation strategy, collaborating closely with architecture and RTL teams to evaluate timing, power and area trade-offs and drive scalable implementation solutions for complex SoC programs. Provide technical leadership for subsystem implementation, guiding floorplan architecture, methodology decisions and timing closure strategies while collaborating across PD, RTL and STA teams. Previously worked on major silicon programs at: Samsung Electronics Ericsson Advanced Micro Devices Core Expertise • RTL-to-GDS physical design implementation • PPA optimization and design convergence • Floorplanning and macro architecture • Early design feasibility and implementation strategy • Power grid planning and EM/IR analysis • Placement optimization and congestion mitigation • Clock tree synthesis and MCMM timing closure • Hierarchical SoC implementation and physical signoff