Rhushikesh Prabhune
ML Hardware Architect @ Arm
About
Skill Set: Computer Architecture: CPU Microarchitecture, Memory sub-system, Branch Prediction, Memory Dependence Prediction, Value/Address Prediction, SMT, Single-ISA heterogeneous multi-core processor, reconfigurable processor, GP-GPU architecture. Compilers: LLVM API, VLIW, profiling, code generation, static scheduling, and compiler optimizations. Operating Systems: Multi-threading, Synchronization, Virtual Memory Systems, CPU Scheduling, Storage, and File System, Drivers.
United States
San Jose
Computer Hardware
C++, C, LLVM, Verilog, Python, C (Programming Language), Computer Architecture, x86 Assembly, High Performance Computing (HPC), Compiler Optimization
Experience
ML Hardware Architect
Arm
San Jose, California, United States
CPU Architecture and Performance Engineer
Qualcomm
Santa Clara, California, United States
CPU Perf Modeling (Rename Unit) @ Nuvia
Remote Intern
Télécom SudParis
Évry, Île-de-France, France
Research Intern
Télécom SudParis
Évry, Île-de-France, France
Research Assistant
Indian Institute of Science (IISc)
Bangalore
Education
North Carolina State University
Computer Engineering
Courses: Microprocessor Architecture Architecture of Parallel Computers ASIC & FPGA Design using Verilog Advanced Microarchitecture GP-GPU Architecture Compiler Optimization and Scheduling Operating Systems Design Design and Analysis of Algorithms Computer Networks Neural Networks
Birla Institute of Technology and Science, Pilani
Birla Institute of Technology and Science, Pilani
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