Rajeev Kumar
Engineer, CPU Design and Methodology
United States
Santa Clara
Semiconductors
VLSI, Physical Design, Static Timing Analysis, Verilog, ASIC, RTL design, Primetime, Timing Closure, Logic Synthesis, Low-power Design, EDA, SPICE, Synopsys tools, C, Very-Large-Scale Integration (VLSI), Application-Specific Integrated Circuits (ASIC), Cadence Encounter
Experience
Engineer, CPU Design and Methodology
Apple
Cupertino, California
Engineer
Broadcom
Irvine
Physical Design and Sign-off of High Performance ARM CPUs and CPU Sub-system Logic on Advanced Process Nodes.
M.S. in Computer Engineering
Texas A&M University
College Station, Texas
Summer Intern CAD
Samsung Austin R&D Center
Austin, Texas Area
Design Engineer
Arm
Engineer
Conexant
RTL design and Verification.
Education
Texas A&M University
Computer Engineering
THESIS: An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and Discrete Fourier Transform (DFT) Courses Taken: Physical Design Automation Introduction to Optimization VLSI Circuits Modelling Computational Methods for Integrated Circuits Design Introduction to Algorithms Advanced Computer Architecture Advances in VLSI Circuit Design Machine Learning
Indian Institute of Technology, Guwahati
Electronics and Communication Engineering
Rajeev Kumar's Contact Information
Phone
Find the Right Leads
Find Verified Contact Data
What LeadContact does well
Find verified emails, phone numbers, and decision-makers with 98% accuracy.
Find Leads
Find the right people by company, role, industry, location, and more.
925M+ professional profiles
Find Emails
Access verified email addresses for your target contacts.
657M+ emails
Find Phone Numbers
Get cross-validated phone data from multiple top sources.
239M+ phone numbers
More Accurate. Lower Cost.
Find contact data in 1 tool with 98% accuracy
LeadContact integrates leading enrichment tools to deliver more accurate contact data—without paying for each one.
Great conversations start with the right contact.
It’s time to find yours.