Rafael Peña Bello

Methodology development and Project support in following areas: - Functional verification UVM/OVM - System Level emulation & FPGA validation - Flow development Perl, Python, Java

- Development of different VIP’s in System Verilog using OOP and internal developed Base Classes (like OVM) - Collaborate in SOC Testbench development by extending the Base Classes with new ones to support the back-door loading of memories - Random stimuli development and Coverage analysis with vcs - VIP Fault analysis usign Certitude - FPGA pre-silicon Validation. Developed the FPGA Flow for pre-silicon validation and software enablement. Created Hard-Macro replacements and successfully synthesized different SOC’s - Design of the digital wrapper for different analog modules Areas: System Verilog(design), CDC, Formal Verification, SVA

Digital Designer. Design of special circuitry (in FPGA or CPLD) for specific Systems on a Board including microcontrollers, FPGA/CPLD and different I/O standards (like LVDS)

Diploma thesis in the Microelectronics Institute from the TU-Darmstadt: Entwurf eines “Rapid Prototyping” Systems fu ̈r Sigma-Delta Modulatoren mit geschalteten Kondensatoren. Areas: A/D Umsetzung, VHDL, Synopsys, FPGA(Xilinx), Java