Lifu Chang, Ph.D.

Managed central Design For Manufacturability (DFM) of 5G mobile application processor SOC, artificial intelligence processor, 5G wireless communication network processor, cloud server processor, etc., at process technologies of 16/12 nm FinFET, 7nm FinFET, 7nm FinFET-EUV, and 5nm FinFET-EUV.

• Manages central DFM Team for all product designs at process technologies of Logic/RF/Analog 28nm CMOS Poly-SiON, 28nm CMOS HKMG, 22nm SOI, 20nm CMOS HKMG, 14nm FinFET, 14nm FinFET-RF, 10nm FinFET, 7nm FinFET, and specialty technologies 180nm BCD PMIC, 180nm CSOI. • Establishes and manages DFM plan-on-record and engineering standards of foundry tapeout sign-off across Qualcomm mobile device products, including SOC Platform, Mobile Processor, Modem, Server Processor, Wireless Transceiver, Power Management IC, Low Noise Amplifier, etc. with multi-million wafer volumes and multi-billion-dollar annual revenues. • Enables and maintains DFM software tool flows for areas of foundry-standardized process margin prediction, yield prediction, and DFM/yield hot spot detections. DFM flows include Smart Fill, Litho Check, Pattern Match, DFM Score Meter, Via Redundancy Check, Redundant Via Insertion, CMP Check, Critical Area Analysis, and Layout Dependent Effect (LDE) API. • Develops, enables, and maintains DFM software tool flows for areas of performance yield parameter requirements and specs, yield lesson learned, and corresponding restrictive design rules. DFM flows include Custom Fill for timing sensitive critical nets, Custom Fill for Vth variability restrictive design rules, Custom Fill for inductor devices, for chip-package-interaction under-bump metal/via density requirements, Power/Ground net via insertion. • Leads, develops, and enables DFM Pattern Analysis and Risk Assessment flows to extract layout pattern libraries and perform detailed OPC litho simulation on patterns, at 10nm FinFET and 7nm FinFET technologies. The flow is an industry DFM initiative to enable early OPC process risk assessment on layout patterns that are new, unique, and not previously seen by the fab DFM flow. • Manages, designs, measures, and analyzes DFM Hard Macro for wafer-test based DFM and yield learning on 14nm FinFET, 10nm FinFET, and 7nm FinFET technology testchips.

Manage the R&D and technical deliveries of the following areas of technology modeling and simulation: (1) DFM (Design For Manufacturability) (2) Design Rules (3) TCAD (Technology Computer Aided Design) (4) Reliability (5) Layout Engineering (6) Software Engineering (7) Information Technology

Taught graduate school classes about On-Chip Interconnect Modeling, Advanced VLSI Circuit Analysis, etc.

(1) Led R&D in DFM (Design For Manufacturability) software tools and developed patents for building technology infrastructures (2) Performed software programming of the DFM software tool for EDA (Electronic Design Automation) applications

R&D of timing and noise analysis

R&D of RLC extraction tools for advanced logic and analog/mixed-signal designs. Interconnect characterization, modeling, and simulation. R&D of static timing analysis. Published more than ten industry-leading technical papers and foundational patents

Participated in group meetings about modeling standard proposals, conference/seminar coordinations, and other tasks assigned by FSA or initiated by the Committee