Jinho Shin

Contribute to RTL design and system-level architecture for automotive AR-HUD SoC Support system-level validation and debug across RTL, FPGA, and silicon behaviour Collaborate closely with verification and system teams to ensure functional correctness Perform FPGA-based prototyping and failure analysis for early system validation Provide technical feedback to architecture and system teams based on validation results

Led RTL design and SoC development for image sensor and mixed-signal SoC products Delivered multiple silicon programs from architecture through to production release Collaborated with verification teams on testbench integration and functional debug Performed system-level failure analysis across simulation and silicon validation phases Drove design improvements through power, performance, and area optimization techniques Contributed to successful tape-outs in both consumer and automotive domains

Designed RTL for camera subsystem and image processing SoCs in mobile application processors Developed key IP blocks including MIPI CSI-2 RX, DMA engines, scaler, and ISP-related modules Led system integration across ISP, DSP, ARM CPU, and AMBA bus architecture Supported full-chip simulation, gate-level verification, and silicon debug activities Worked closely with verification teams using UVM-based environments for functional validation Performed architecture-level debugging across ISP and processor subsystems

Developed RTL design for multimedia SoC and image processing IPs Designed peripheral IPs including I2C, SPI, and UART controllers Participated in FPGA prototyping and system-level validation Supported silicon bring-up and functional debugging activities Performed simulation-based verification and issue resolution at RTL level