J++ Liang

ASIC Design Verification Engineer @ Google

About

• Design Verification leader with extensive hands-on experience in pre-silicon verification and post-silicon validation for SoCs, ML Accelerators , GPU, SMMU, Bus interconnect and memory controller.• Experience in building elite verification team for IPs and people management. • Specialties: Testbenches in SystemVerilog/UVM/OVM, Formal Verification, Vera RVM/QVM, SystemC, C/C++, Verilog, VHDL, AMBA AXI, AHB, SVA Assertions. • Simulators: VCS, IUS, MTI • EDA Tools: PowerArtist, Synopsys RTL Architect, Design Compiler, JasperGold, VC Formal, Verdi, DVE, Mentor Certe, AMIQ DVT

Country

United States

City

San Francisco Bay Area

Industry

Semiconductors

Skill

Verilog, SystemVerilog, Functional Verification, SoC, ARM, Processors, VHDL, ASIC, Debugging, C++, Testing, Embedded Systems, C, Shell Scripting, Perl, FPGA, Device Drivers, UVM, Formal Verification, SMMU

Experience

ASIC Design Verification Engineer

Google

2026-4 - Present · 6 mos

San Francisco Bay Area

Google Cloud TPU team advancing the next generation of AI chips.

ASIC Design Verification Engineer

Senior Design Verification Engineer

Amazon Lab126

2020-6 - 2021-10 · 1 yr 5 mos

San Francisco Bay Area

Machine Learning Neural Network Accelerators verification

ASIC Design Verification Engineer

Intel

2016-4 - 2020-6 · 4 yrs 3 mos

San Francisco Bay Area

• Verification Architecture Engineer at SDG, developed highly configurable and reusable verification infrastructure for Xeon Scalable CPUs in SystemVerilog, OVM/UVM and C++. • Code review all developers’ changes, managed releases and waterfall branching mechanism.

ASIC Design Verification Manager

Qualcomm

2009-1 - 2016-3 · 7 yrs 3 mos

Toronto, Ontario, Canada

• Lead Design Verification teams for Multimedia bus interconnects, ARM SMMU, delivered over 100 configurations to Snapdragon SoCs, with two of SoCs have sold over 200 million units. • Lead developing cycle-estimated, transaction accurate bus interconnect C-models for SoC testing. • Performed bus certification on proprietary and AXI bus interfaces with formal verification, SVA proof kits. • Lead the team transition from Vera test bench to SystemVerilog/UVM test bench. • Involved in DV methodology initiatives, worked with EDA vendors to evaluate leading edge formal verification technologies (Cadence JasperGold vs Synopsys VC Formal), SystemVerilog and UVM coding linters.

ASIC Design Verification Lead

AMD

2006-10 - 2009-1 · 2 yrs 4 mos

Toronto, Canada Area

• Lead developing Imageon Memory Controller verification infrastructure, a SystemC, Verliog test bench for A250, A280 mobile application processors. • Convert testbench from Cadence tools to Synopsys tools. Debugged tool issues with Synopsys R&D, awarded several Synopsys STARs.

ASIC Post-Silicon Validation Lead

AMD

2003-10 - 2006-10 · 3 yrs 1 mo

Toronto, Canada Area

• Lead diagnostics effort to successfully bring-up Imageon 2260/2262, 2182, 2282, 2388/2380 processors in Handheld Division of ATI Technolgies Inc. • Designed and developed test cases to verify the GPU, Command Processor, Memory Controller (MC), Audio and Video IP blocks.