Ifar Wan

* Drove the GPU Silicon Validation team in San Diego from the emulation phase to high-volume production to successfully commercialize Qualcomm's premium-tier SOC mobile chips. * Worked with cross-functional teams in our design, validation, test, SW and program management domains to constantly improve the product performance and perf/Watt KPIs on actual silicon, to debug and implement solutions for system-level SW failures, and at the same time, to ensure a low DPPM product for our customers.

* Led the GPU Silicon Validation team for Qualcomm's premium-tier SOC mobile chips. * Involved in the commercialization phase of the products, from the FPGA emulation to the first silicon bring-up and thru the high-volume chip production. * Key responsibilities included the functional validation of the GPU IP core and its firmware, the enablement and tuning of the special power management features, the power and performance analysis on a bare-metal test environment with full system components, and debug of SW-related system level failures.

* Wrote the silicon validation testbench in embedded-C and owned the testplan for the validation of our power management and the GPU firmware code using a JTAG-based bare-metal system test platform. * Delivered functional tests for the production ATE and system platforms and worked with the test engineering teams to resolve yield issues on their platforms and to analyze silicon data over PVT (process, voltage, temperature). * Debugged and root-caused several critical functional issues found by our internal SW and external test teams.

* Responsible for the characterization and performance assessment of our cache memory cells in the latest IA microprocessors during their product life cycle. * Responsible for creating the test content and defining the test flow requirements for our embedded DRAM product, pursuing TTR and ensuring both high-coverage and low DPM during High-Volume Manufacturing. * Responsible for the design verification and validation of our memory DFT features during pre-Si with regression tests written in Specman language. * Worked closely with designers, Q&R and Yield engineers to influence changes in DFT circuits to meet or improve our test requirements and to ensure both product and process quality until maturity.

* Worked on a variety of projects in the area of Silicon Debug and Failure Analysis on several generations of Intel IA32/64 microprocessors and SOC circuits. * Daily work entailed using high-speed and structural testers to analyze and root-cause Yield defects and circuit bugs in the logic, memory and I/O blocks. * Obtained extensive knowledge in many industry-standard and custom DFT features: TAP, ATPG scan, BIST, boundary scan. * Wrote extensive PERL scripts and advanced C/C++ object-oriented programs that communicated with testers, extracted important data from DUTs and provided solutions for automated data collection and data analysis during debug.