Hiranmai Batte
Verification Engineer @ Intel Corporation
About
-Graphics hardware Verification Engineer at Intel. -Masters in Electrical Engineering from San Jose State University.
United States
San Jose
Computer Software
Regression Testing, Graphic Design, Graphical User Interface (GUI), Optical Fiber, Network Security, Networking, Virtual Private Network (VPN), Wide Area Network (WAN), FPGA prototyping, Floating Production, Storage and Offloading (FPSO), Logic Gates, EDA, MATLAB, Mathworks, GNU Octave, Octave, MIPS Instruction Set, Microprocessors, Functional coverage, Constraints
Experience

Student Intern
Bharat Sanchar Nigma Limited
India
Vocational trainee in telecom
Education

Electrical Engineering
Relevant courses: Probability,Random Variables and Stochastic Processes (EE 250) Advanced Digital System Design and Synthesis (EE 271) Advanced Computer Architecture (EE 275) CMOS SoC design, and verification with System Verilog (EE 272). Internetworking (EE 281). Digital Design for AI and DSP (EE 278). Computer Vision with Artificial Intelligence Applications (EE 267). Network Security (EE 209).
Hiranmai Batte's Contact Information
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