David Lacey

Working on software infrastructure for AI/ML research

Directed the architecture and design of software at Graphcore. Created a new software roadmap to address customer needs by working with the software engineering team and product management to create new technical solutions and developing proof-of-concept prototypes to answer key questions on how the backend of Graphcore’s ML frameworks (TensorFlow, PyTorch) can be improved. Helped define the next generation of Graphcore hardware by working in conjunction with the silicon and system architecture teams, modelling use cases and designed software structure to work with the new hardware. Encouraged more external engagement for low-level use cases by introducing a programme to work with key academic partners on novel uses of Graphcore hardware (the “accelerated computing academy”)

Built a worldwide engineering division to support customers by training users on Graphcore technology, debugging and solving customer issues and running joint engineering projects with customers. Grew a team from scratch to 50+ engineers including recruiting for both engineering and key management positions, mentoring and directing work among the team and setting up process and working methods across a diverse multi-region and multi-timezone team. Directed the creation of Graphcore's reference application and benchmark suite to support the hardware and software product and provide a base for customer development. Worked with several high-profile customer engagements and project life-cycles to ensure successful progression of key customer projects.

Starting from the beginning at Graphcore, I acted as as technical lead on the development of Graphcore software to ensure we had a development platform for the Graphcore IPU that allows our users to easily write software that delivers state of the art performance and aided in the building up of the software team. My work involved working with the software team to create a software stack that could target the Graphcore IPU - a brand new type of parallel processor. This project required creating a usable framework for developers that also provided the highest possible performance on the hardware. The implementation had to blend aspects of machine learning, compiler development, high performance computing and plain old decent software engineering. During the process (and as the team grew), I made many contributions to the development of the Poplar C++ library and associated application libraries (including complex linear algebra and machine learning kernels) alongside running design meetings, development planning and technical mentorship of software developers.

Worked as a software developer within the tools team working on infrastructure, compiler development and application libraries. Working as technical lead for the last 5 years. During my time at XMOS work has included: • Maintaining the tools technology roadmap, including responsibility for investigating new technologies for use in the XMOS development tools and carrying out feasibility studies in potential new areas. • Responsibility for producing technical outbound marketing material: papers, technical blogs etc. • Acting as design lead on several software projects (compiler and development toolchain, software component exploration GUI tools and application libraries). • Migrating continuous integration and release infrastructure to AWS cloud deployment (including the investigation and deployment of various technologies including AWS, Docker, Nginx, OAuth2, Django, Buildbot, CDash and Phabricator). • Leading a cross-team effort to improve the quality and consistency of application development (development of coding standards, process, QA and documentation standards). • Acting as lead developer maintaining and implementing optimizations for the company's xC (a variant of C) compiler through several release cycles. The optimizations implemented were both generic compiler optimizations missing from the internally developed compiler and processor specific optimizations relating to the I/O architecture of the target device. • Acting as lead developer for the Ethernet AVB Reference Design. Work involved developing the code, implementing newly developed IEEE standards, managing requirements for the reference design, attending interoperability plugfests and carrying out customer support around the design. Worked as a "troubleshooter" towards the end of the production cycle of a USB Audio reference design to help get first customers through to production.

I was a member of the SDK team. Worked on the compiler (particularly on optimizations within the compiler) and implemented high performance math libraries (libm functionality) on the Clearspeed platform. Also worked on other projects such as computational finance applications, compiler benchmarking and some micro-architecture work.

Faculty position, lecturing, research, teaching and admin. ● Revised course materials and taught first year functional programming ● Added modern compiler design to the curriculum by developing and teaching new masters level advanced compiler design course. ● Established the base for research for formal verification of compilers including obtaining EPSRC grant for the subject

Phd in optimizing compilers.