chamundi P.
pre silicon verification Engineer @ Intel
About
With over 8 years of experience in pre-silicon and design verification, I have contributed to the development and validation of IPs in the semiconductor domain, using SystemVerilog, OVM, and UVM. My most recent role at Intel Corporation involved working on IP design verification in the CXL domain, where I collaborated with cross-functional teams to ensure robust and reliable designs. My professional journey spans roles at NVIDIA and Intel where I specialized in FPGA-based IP verification and circuit design with scripting expertise. I am passionate about leveraging my technical skills to contribute to high-quality hardware development while maintaining a focus on innovation and precision.
United States
San Francisco Bay Area
Electrical & Electronic Manufacturing
SystemVerilog, OVM, UVM, Functional Verification, System on a Chip (SoC), Technical Engineering, Debugging, Test Planning, Cadence Virtuoso, Cadence Virtuoso Layout Editor, Cadence Spectre, Animal Models, Eclipse RCP, Eclipse, Java, Matlab, PSpice, Microsoft Office, VLSI, Linux
Experience

Graduate Teaching Assistant (Mentor) for VLSI system design
Greater Los Angeles Area
• Designing labs, home works and conducting discussion sessions to help students to understand the concepts • Working on circuit design, layouts along with Perl scripting for automating tasks

Programmer Analyst Trainee
•Worked as Java programmer on automation tool design, ADPART4.0 (Activity Diagram-Based Path Analysis and Regression Testing) on Eclipse RCP platform Eclipse plugin development and designing. •Developed a part of the UI for ADPART4.0 using SWT and JFace components and also implemented the back-end functionality for the same module.
chamundi P.'s Contact Information
Phone
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