chamundi P.

chamundi P.

pre silicon verification Engineer @ Intel

About

With over 8 years of experience in pre-silicon and design verification, I have contributed to the development and validation of IPs in the semiconductor domain, using SystemVerilog, OVM, and UVM. My most recent role at Intel Corporation involved working on IP design verification in the CXL domain, where I collaborated with cross-functional teams to ensure robust and reliable designs. My professional journey spans roles at NVIDIA and Intel where I specialized in FPGA-based IP verification and circuit design with scripting expertise. I am passionate about leveraging my technical skills to contribute to high-quality hardware development while maintaining a focus on innovation and precision.

Country

United States

City

San Francisco Bay Area

Industry

Electrical & Electronic Manufacturing

Skill

SystemVerilog, OVM, UVM, Functional Verification, System on a Chip (SoC), Technical Engineering, Debugging, Test Planning, Cadence Virtuoso, Cadence Virtuoso Layout Editor, Cadence Spectre, Animal Models, Eclipse RCP, Eclipse, Java, Matlab, PSpice, Microsoft Office, VLSI, Linux

Experience

Intel

pre silicon verification Engineer

Intel

LinkedIn
2021-11 - 2024-10 · 3 yrs

Working as IP design verification Engineer in CXL.

NVIDIA

Pre silicon verification Engineer

NVIDIA

LinkedIn
2021-6 - 2021-11 · 6 mos

Santa Clara, California

Worked as IP verification Engineer in a FPGA team

Intel

Design Verification Engineer

Intel

LinkedIn
2016-7 - 2021-6 · 5 yrs

Santa Clara County, California, United States

University of Southern California

Graduate Teaching Assistant (Mentor) for VLSI system design

University of Southern California

LinkedIn
2015-8 - 2015-12 · 5 mos

Greater Los Angeles Area

• Designing labs, home works and conducting discussion sessions to help students to understand the concepts • Working on circuit design, layouts along with Perl scripting for automating tasks

Cognizant

Programmer Analyst Trainee

Cognizant

LinkedIn
2013-10 - 2014-6 · 9 mos

•Worked as Java programmer on automation tool design, ADPART4.0 (Activity Diagram-Based Path Analysis and Regression Testing) on Eclipse RCP platform Eclipse plugin development and designing. •Developed a part of the UI for ADPART4.0 using SWT and JFace components and also implemented the back-end functionality for the same module.

Education

University of Southern California

University of Southern California

LinkedIn

Electrical Engineering , VLSI

2014 - 2016 · 2 yrs

chamundi P.'s Contact Information

Email

******@***.com

Phone

(**) *** ****

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