Avro Mukherjee
Senior RTL Integration Engineer @ Samsung Semiconductor
About
Senior RTL Integration Engineer weaving Samsung’s premium GPU silicon into high‑performance SoCs—and having a little too much fun doing it. I live at the intersection of RTL integration, ASIC flow, DFT methodologies, and automation, turning messy reality into clean, implementation‑ready RTL through obsessive build flows and regression infrastructure across Lint, CDC, VCS, LEC, and synthesis. Fluent in Verilog, Python, TCL, shell scripting etc. I enjoy bending complex GPU tiles, congestion, and placement to my will—but the real obsession is using man‑made tech to push human capabilities forward, not just close the next tape‑out.
United States
San Jose
Semiconductors
RTL Development, Red Hat Linux, Cloudbees, Jenkins, Git, Perforce, Synopsys tools, Cadence tools, Floorplan exploration, Comnectivity Analysis, Block synthesis tool, Conformal LEC, EDA, DV Infra, Microarchitecture, Verilog, Python (Programming Language), C (Programming Language), Application-Specific Integrated Circuits (ASIC), Programming
Experience

Intern
Samsung Austin Semiconductor
Austin, Texas, United States
Work Roles and Projects: • Debugging stuck at and transition faults using Verdi and Tetramax(Fault modelling) • Testbench verification and debugging using Verilog and system Verilog • Adding repeater flow to the chip design to meet timing constraint, using SPYGLASS to validate the connections. • Developed python scripts automating test access mechanism and spf file insertion tool during ATPG • Building on Repeater planning tool development using TCL and python developed by previous intern • Documenting design methodologies and work cases enriching knowledge base for future hires • Developing a ATPG patgen to test coverage to Simulation flow automated report monitoring key flow points that will assist in debugging.

Graduate Research Assistant
Hoboken, New Jersey, United States
Graduate Research Assistant/DOMAIN - VLSI CELL PLACEMENT TECHNIQUES • NVIDIA’s Open source project Dreamplace configuration and validation using NTUPLACE3 Algorithm for analytical placement • Research involves studying and understanding various VLSI cell placement techniques to increase efficient of developed placement algorithms OPEN SOURCE PROJECTS Project 1: Placement Problem Testing and Verification Open Source Tool Used:DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement Demonstrated 30% speedup in global placement and legalization. Project 2: No Human Intervention EDA Project (RTL to GDSII designing) Open Source Tool: OpenROAD Project - A full RTL-to-GDS flow. Complete automated process achieve in cup design phases. Project 3: RISC-V Core Development Project Open Source tool: Darkrisc-V - RISCV ISA. works up to 100MHz (spartan-6) and sustain 1 clock per instruction most of time Tools used to simulate and synthesis: Xilinx ISE 14.7

Summer Research Student
United States
RESEARCH EXPERIENCE - Honors Summer Research Program Student Summer Research Intern Topic: Improve efficiency of Nano-Scale Circuits Well-designed circuits are becoming more complex due to decrease in size. As we move forward into the nanoscale regime, circuit design is burdened with more intrinsic challenges and restraints. My work is on researching to explore this field and come up with solutions that can increase design efficiency. Work in areas with new techniques for logic circuits and interconnect, for memory, and for clock and power distribution and survey work to build accurate simulation models for nanoscale devices.I work with open source chip verification and placement design tools in an efforts to model, analyze, and optimize designs with ever increasing amounts of statistical variation to tackle the challenges with nano scale design poses. My current roles and responsibilities: • Establishing cell placement benchmarks for detailed and global placements on ISPD Benchmarks using DREAMPlace: Deep Learning Toolkit – GPU acceleration for modern VLSI Placement. • Debug using phases of physical design devemopment including parasitic extraction, static timing, wire load models, clock generation, packaging and verification. Utilized innovus to verify placement, optimization and routing design validation checks. • Developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure for designs provided by advisor. • Working on opensource Electronic Design Automation tools such as EDA FLOW, OpenROAD, released by University of California, San Diego for design verification of RTL to GDSII design cycle • Experience in simulating and validating the design in model sim on VHDL codes. Designing and writing test benches for 4 bit Full Adder, SRAMS, Comparator, Encoder and Decoder in ModelSim using Verilog

Project Manager Business Development
Noida, Uttar Pradesh, India
Projects Handled: • Managed Crescent hospitality’s North American portfolio consisting of more than 200 properties managing production escalations, deployment scheduling, customer relations and new enhancements. • Oversaw and coordinated leading procure to pay software solution to 15 hotel locations for Island Hospitality in North America region. Budget for each hotel ranges from $20,000 to $35,000 with similar amount in yearly subscriptions. • Supervised and managed ORACLE integration for HEI hospitality, automating their North American hotel procurement system consisting of more than 90 hotels with Birchstreet Systems and ORACLE integrating seamless invoice management, purchase Order management and budget management. The project lasted for more than one year and had a budget of $100,000. --> Spearheading functional document creation for new integration setups for Marriott. --> Presenting the new design to the Marriott and Accenture team for them to validate the proposed process. --> Taking up new design requirements on meeting and incorporating them to the new functional designs. • Integration Project management: I was made responsible for managing the integration team. Below roles and responsibilities handed over to me: 1. Customer/Internal communications: --> Understanding/documenting requirements for new integrations. --> Doing demonstrations on existing interfaces to clients and stakeholders. 2. Aligning technical resources (during requirement gathering phase) for any custom/special integrations needs wherever required. --> Identifying new requirements and assigning technical resources to complete the design document. 3. Monitoring/Prioritizing the integration-related action items (Maintaining JIRA Board with due dates) --> Updating progress to clients/internal stakeholders on project movements. --> Raising flags internally wherever required / Seeking information from involved individuals/teams.

Assistant Manager
Noida Area, India
Manager handling a team of 7 Solution Engineers/Analysts working on highly complexed and technical issues. • Planning and assigning of tasks among various team members and auditing the solution and delivery rate. • Providing technical and functional guidance on application and modules to team members. • Identifying project risks at the early stage and taking necessary actions by informing the concerned person and developing case scenarios. • Building a self-sufficient and independent team that can handle anything and everything which is thrown at them. •Documenting all code changes, verification methods that help testers to test functionality, and report bugs. •Collaborated with the control systems, simulation, and modeling teams to design control strategies that can be implemented in software efficiently. Resolved bugs, propagated changes, verification, and developed features. •For each developed feature and design, implemented a corresponding test framework to verify functionality. •Assisting Genpact team with their dally AP invoicing data from Birchstreet, and actively resolving the issues faced by them. •Setting up an integration network and directories for the flow of invoices from the back-office payment systems like people-soft, Sun, SCALA to hotels.

Senior Analyst / Escalation Engineer
Noida Area, India
• Discussing possible new features with other teams, analyzing solutions on PTRs, regressive testing on QA and UAT environments. • Take Webex sessions with clients to fully grasp the scope of issue, and provide possible fix, or workaround. • Integration setup and configuration for newly added properties, and providing technical solutions, and detailed incident reports to customers facing issues, due to existing task schedulers and integrations. • Documenting all code changes, verification methods that help testers to test functionality, and report bugs. • Collaborated with the control systems, simulation, and modeling teams to design control strategies that can be implemented in software efficiently. Resolved bugs, propagated changes, verification, and developed features. • For each developed feature and design, implemented a corresponding test framework to verify functionality.

Analyst/Engineer
Noida Area, India
• Devised a complex report structure using Oracle’s database management tool for Hilton Hospitality’s CAPEX tracking using MySQL • Project IR sensor: Developed IR sensor driver that reports capabilities and receives input from a remote device and converts key events to commands, and interacts with the android HAL layer to send events to upper layers • While working on features, coordinated with hardware design engineers to provide effective system solutions. Code-reviews, suggesting improvements, analyzing core dumps and stack frame to find the root cause of the issue. • OpenGL: Experience with C/C++ and low-level graphics OpenGL APIs interaction with the userspace display driver. • Collaborated with the control systems, simulation, and modeling teams to design control strategies that can be implemented in software efficiently. Resolved bugs, propagated changes, verification, and developed features.
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