岳霆林

R&D Principal Engineer (3DIC central team) @ TSMC

About

Work Experience: 3DIC R&D process integration engineer of working in the leading company in semiconductors industry.- 14+ years experience on advance package - 4 years' experience of 3DIC Design Rule / Test Vehicle design - 7 years' experience of 3DIC Packaging Integration - 3 years' experience of APC / AOI solution development- Being familiar with CoWoS/InFO/SoIC technology and design rule- 8+ US patentsPatents:US10720409B2, US11177142B2, US10867928B2, US20240055311A1,US11587900B2, US11088094B2, US20230068082A1z, US10756037B2Awards:2025 Golden Trade Secret Award2020/2025 Special Award2022/2023/2024/2025 RD IIP(Integrated Interconnect & Packaging Engineer) Contribution Award

Country

Taiwan

City

Hsinchu City

Industry

Semiconductors

Skill

問題解決, Bump, Packaging Engineering, IC Layout, PCB 設計, Manufacturing Process Improvement, 資料分析, 3DIC, 可靠性, 故障分析, Matlab, Design Rule Checking (DRC), 自動化, 製程, 研究與開發 (R&D), 人工智慧, 半導體, 决策, 压力大的情境, 公开演讲

Experience

R&D Principal Engineer (3DIC central team)

TSMC

2022-1 - Present · 4 yrs 9 mos

台灣 Taiwan 新竹市

Successfully developed CoWoS-S/CoWoS-L/InFO-PoP/InFO-oS design rule for mass production. Lead team to develop CoWoS-R/CoW-R/SoIC/SoW/Automotive InFO-oS design rule for Test Vehicle design. Collaborate with internal teams to develop and arrange customer's design collateral request (DRC, LVS, APR, RC, Interface deck...) Collaborate with tier1 customer to overcome design challenges tomeet customer's design requirement with manufacturing capability.

R&D Senior Engineer (InFO Integration Program）

TSMC

2015-1 - 2022-6 · 7 yrs 6 mos

台灣 Taiwan 新竹市

CoWoS-L baseline development and successfully led cross-functionteams to build up oS loop process baseline. Collaborated with tier1 customer to develop InFO-PoP baseline and InFO-M-PoP baseline. Successfully developed 3DIC wafer map methodology and system to enable asymmetry wafer map for productivity improvement. New material evaluation and implement in mass production.

R&D Engineer (Advanced Control Program）

TSMC

2011-10 - 2015-1 · 3 yrs 4 mos

新竹

Coordinated cross-function teams and successfully developed PVD/Litho APC (Advanced Process Control) and AOI (AutomatedOptical Inspection) system for 3DIC manufacture to improve process capability and people productivity.