
苏婕 苏
SMIC CE @ SMIC
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China
Semiconductors
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Experience

Failure analysis engineer
BJ & SH
Paper (First author and co-coworker): a. Electrical Signature Verification of a Lightly Doped Drain Profile Abnormality in a 65nm Device via Nano-Probing and Junction Stain TEM. 35th International Symposium for Testing and Failure Analysis November 17-19, 2009, McEnery Convention Center, San José, California, USA b. Al Pad Corrosion Mechanism Study when Dicing Saw. 33rd International Symposium for Testing and Failure Analysis. November 4-8, 2007, McEnery Convention Center, San José, California, US
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