大石周大石

ChangXin Memory Technologies, Inc. - Director @ ChangXin Memory Technologies, Inc.

Country

China

City

Shanghai

Industry

Semiconductors

Skill

Directors, Technology Evaluation, Process Improvement, Semiconductor Process, Director level, Semiconductors

Experience

Director

ChangXin Memory Technologies, Inc.

2023-8 - Present · 3 yrs 2 mos

合肥

Director

SmartSens Technology 思特威科技

2020-8 - 2022-8 · 2 yrs 1 mo

中華人民共和国シャンハイ市

Built up FSI platform technology in partner fab for Smartsens product from the scratch. Built up BSI platform technology in partner fab for Smartsens product from the scratch. Building up sub-um pixel technology in partner fab for Smartsens product.

Deputy Director

Huaian Imaging Device Manufacturer

2017-7 - 2020-8 · 3 yrs 2 mos

江苏省淮安市

Platform development procedure & work flow construction for start up company. Management of platform development on 1.12um planer & 1.0um 3D stack sensors.

Senior Manager

Imaging Device Technologies Corporation

2016-4 - 2020-8 · 4 yrs 5 mos

先端ロジックデバイス開発

Toshiba

2007-4 - 2016-3 · 9 yrs

横浜、大分

2013.4-2016.3 TOSHIBA Advanced Image Sensor Device Development center (Chief Specialist) 0.98um Silicon platform technology development manager. Leading edge pixel development with R&D center & university. 2011.4-2013.3 TOSHIBA Image sensor device development department (Specialist) 0.92um Silicon platform technology leader. R&D on pixel performance boosters as vertical gate、BDTI and clear pixel. 2007.4-2011.3 TOSHIBA System LSI device development department (Specialist) 40nm SoC transfer to fab & pilot product ramp up Completed platform development in pilot line and set it up in fab for production. Analyzed standby power consumption issues & handled it for yield enhancement. 40nm logic Si technology setup in Samsung Electronics for outsource Handled difference of design rules, FET characteristics and reliability issues. Operation speed issue is solved based on on-chip variation analysis.

先端ロジックデバイス開発

Toshiba

1996-4 - 2006-3 · 10 yrs

横浜、大分

2004.4-2006.3 TOSHIBA System LSI device development department (Specialist) 40nm SoC front end process & device development leader Completed platform development of 40nm SoC in pilot line collaborating with SONY & NEC. Developed FET booster techniques both for low standby power & high performance FET. 1996.4-2004.3 TOSHIBA Microelectronics development laboratory (Engineer) 40nm SoC front end process & device development 90nm SoC front end process & device development 0.18um high performance FET development (deployed in PlayStation)

Education

Massachusetts Institute of Technology

Microelectronics technology lab

2006 - 2007 · 1 yr

2006.4-2007.3 Massachusetts Institute of Technology (Visiting researcher) Research on ballistic carrier transport in 40nm FET (Prof. Dimitri Antoniadis) Circuit topology study for low standby power (Prof. Anantha P Chandrakasan)