Zubin Jain

• Develop RTL modules using SystemVerilog for NPU architectures, including AXI, APB, PCIe, and systolic array designs for NPUs. • Perform timing analysis and optimization for high-performance hardware blocks. • Lead verification efforts using UVM methodology, including test planning, coverage closure, and model generation. • Automate FPGA workflows using Vivado and TCL scripting. • Built regression and test automation systems using Jenkins, Python, and Perl. • Integrated Claude and Codex into Agentic RTL Workflows.

Working on modeling of new ADC and other VSLI Circuits at ultra-low power.

Developing Pose Detection System for Data Capture