Zhonghao Du

Section Manager of Wafer Process @ AOI

About

Conceive and innovate novel nanodevices based on new III-V semiconductors and 2D materials; Develop and integrate new processes for Si and III-V semiconductors 6+ years hands on experiences in semiconductor fabrication, including lithography, ALD, PECVD, E-beam and thermal evaporation, RIE-ICP, sputtering and wet etch; 6+ years hands on experiences in electrical characterizations and optical metrology instruments, including probe station, C-V, oscilloscope, photocurrent measurements, ellipsometry, FTIR, AFM, SEM EDS and Raman.

Country

United States

City

Sugar Land

Industry

Semiconductors

Skill

Electron Beam Lithography, Photolithography, Stepper, JMP, Klayout, Wet Etching, RIE, ICP, Design of Experiments (DOE), Device Design, Yield Enhancement, III-V, equipment owner, Statistical Process Control (SPC), Dry Etching, Thin Film Coating, Process Engineering, Process R&D, Failure Analysis, TCAD

Experience

Section Manager of Wafer Process

AOI

2026-2 - Present · 7 mos

休斯顿, TX

- Lead a group of 4 engineers and 12 technicians. Supervise the photolithography and E-Beam Lithography process. Oversee the production line daily capacity. - Lead the process development from 1X Mask Aligner to 5X Stepper photolithography. Lead the wafer size scale-up and yield enhancement. - Process integration and layout design for 25G DML/100G EML/1mm CWDM/4mm UHP. - Direct the procurement and qualification of new semiconductor equipment. Manage vendor evaluation, performance benchmarking, process validation, and installation.

Senior Wafer Process Engineer

AOI

2025-5 - 2026-3 · 11 mos

Houston, Texas, United States

- Develop and optimize the lithography process, including grating e-beam lithography (JEOL JBX-8100), photolithography (SUSS MA-6 Aligner, Canon FPA-3030i Stepper). - Use Python to generate mask/reticle layout and BEAMER to optimize the subfield boxing, perform PEC and improve the wafer throughput. - Process integration for 25G DML/100G EML/CWHP (1mm/3mm/4mm cavity length). Data analysis to find the correlation between test data and process deviations. - Statistical process control for process uniformity and consistency. Yield enhancement for high volume manufacturing.

Process Engineer

Hisense Photonics

2024-2 - 2025-5 · 1 yr 4 mos

New Jersey, United States

Process integration on grating, mesa etch and Epi growth as well as metalization for improving the BI performance. Process module owner for the next-generation of high speed data communication product, including 100G EML/High power DFB etc; Process development on new dry etch and wet etch process for III-V laser chips; DOE design for devices development and reliability; SPC control for multiple fabrication process and closely work on yield improvements; Equipment owner of wet etch and RIE-ICP; Material characterization skills: SEM, EDS, XRD, AFM etc

Research Assistant

University of Southern California

2017-8 - 2023-12 · 6 yrs 5 mos

Los Angeles, California, United States

Teaching Assistant

University of Southern California

2019-8 - 2019-12 · 5 mos

Process Development Engineer

Texas Instruments

2023-5 - 2023-8 · 4 mos

Dallas, Texas, United States

Characterize high-voltage power devices by program test and bench test; Used TCAD to simulate breakdown voltage, threshold voltage, leakage current, isolating voltage and so on; Analyzed data statistically to see whether modules match our previous process and design splits; Greatly optimized process flow as well as device structures, reduced the device size by 40%, updated PCD; Design new DOEs and generated new specification files for next test chip