Zheping Yin
Graphics (GPU) RTL Design Engineer @ Apple
United States
Austin
Computer Hardware
Cadence Virtuoso Layout Editor, TCL, Cadence Virtuoso, Python (Programming Language), Integrated Circuits (IC), Analog Circuit Design, Verification and Validation (V&V), Very-Large-Scale Integration (VLSI), Application-Specific Integrated Circuits (ASIC), Accelerator, Physical Design, FPGA prototyping, Raspberry Pi, Research, Electrical Engineering, Java, Engineering, Computer Science, Algorithms, AutoCAD
Experience
Graphics (GPU) RTL Design Engineer
Apple
Austin, Texas, United States
Research Assistant
Georgia Institute of Technology
Atlanta, Georgia, United States
ML Accelerator Design Research at PSy Lab supervised by Professor Sathe
Research Assistant
Lafayette College
Easton, Pennsylvania, United States
Research on CAD algorithm visualization and hardware priority queue supervised by Professor John Nestor
Tutor
Lafayette College
Tutor for Embedded System course
Tutor
Lafayette College
Easton, Pennsylvania, United States
Tutor for Data Structures and Algorithms
Education
Georgia Institute of Technology
Electrical and Computer Engineering
Average tapeout enjoyer
Lafayette College
Electrical and Computer Engineering
International Department of Shude High School
Zheping Yin's Contact Information
Phone
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