Yung-Tai Sun

Silicon Lifecycle Management (SLM)： YieldExplorer account management and feature enhancement Silicon.da account management and applications customized Skill: Data integration, Yield analytics, customer service, tcl, flow automation, Python

• Established the team's first NAND components testing platform with Raspberry Pi and FPGA. • Extended over 20 functions of NAND operation and characteristics plots in a Python-based Macro. • Utilized Jira for internal datasheet tasks management. Edited datasheet by using AEM and FrameMaker.

• Coordinated wafer manufacturing, device simulation conditions, and wafer measurement strategies. • Optimized test-key layout (>500 DUT) and testability using process concepts and CAD tool. Summarized DRC violation details (over 100 rules) using Calibre and risk assessment of waiving DRC before tape-out. • Oversaw products schedule, including production plans, resources arrangement, OPC learning, and tape-out. • Supervised and collaborated with designers and modules for layout modification requests. • Estimated 3D IC and reliability test-key design in AA process, and estimated availability of dummy utility. • Led and mentored new recruits for tool familiarity and professional knowledge using in work.

• Evaluated layout of outsourcing test-key with the design of experiment (DOE) to split over 1000 conditions. • Contributed wafer yield improvement by 10% through process optimization and structure analysis. • Utilized CAD tools such as Virtuoso in Linux environment for layout review and inspection. • Addressed identifying process issues by electrical and physical characterization. • Assisted tape-out procedures and did mask verification through XOR before writing to avoid mask errors. • Delivered two patents for novel semiconductor processes for device boosting and reliability. • Coordinated over 10 continuous improvement plans in the 28 nm platform and reported outcomes weekly. • Lectured a course on semiconductor devices and processes as an internal lecturer, with a total time of over 10 hrs.

• Administered 4 ASIC products including GPU and CPU for high-performance computing needs. Reported weekly product status to customers including AMD and an AI startup Cerebras adopting 7 nm technology. • Collaborated with multiple teams to achieve 4 products with yield >85% (D0< 0.1) from 60%. • Brought up three continuous improvement plans (CIP) via DOE for yield enhancement, output improvement, and cost reduction, each 0.5-2%, with total savings >1 million USD. • Supervised the first 3D IC product in 7nm technology with the TSV technique delivered by the R&D team. • Responsible to flow maintenance, lot handling, and contributed over 10k wafers with yield verification. • Utilized JMP tool to analyze device properties of EVT products (hot carriers effect, Vtrigger, parasitic capacitor/resistance, ring oscillator, break down voltage, leakage...etc) after applying process changes. • Coordinated all BEOL-related issues in the team, including new process evaluation and troubleshooting in inline and device properties. • Conducted failure model studies by data analysis through various inspections (physical properties/ electrical properties/ defect/ yield) and proposed solutions to check results. • Experienced in Statistical Process Control (SPC). Familiar with process maturity indexes such as k/Cp/Cpk. Monthly monitored massive quantity products (>500 pcs/month). • Studied design of test (DFT) concepts such as Scan Chain to address yield loss and physical failure.

I was in charge of Internet marketing survey of popular basketball online games in China and analyzed the pros and cons comparing with the NBA authorized online game. It helped the company to find opportunities to share the market despite of the later entry.

Focusing on the field of: - Digital Design and Layout Verification - Digital Systems Testing and DFT - Computer-Aided Design (CAD) Tools - Computer Architecture - Fundamental Machine Learning

Journal: “A solvent-free lift-off method for realizing vertical organic transistors with low leakage current and high ON/OFF ratio”, Organic Electronics, Vol. 31, Apr. 2016, Pages 227-233 ”Reducing Splicing Loss Between a Silicon-Cored Optical Fiber and a Silica Optical Fiber”, IEEE Photonics Technology Letters, Vol. 28, Aug. 2016, Pages 1774-1777 Conference: “Reducing coupling loss between a silicon-cored fiber and a silica optical fiber”, 20th Micro-optics Conference (MOC’15), Fukuoka, Japan Project: AMOLED Display using Vertical Polymer Transistors with Metal Mesh Gate (Sponsored by Ministry of Science and Technology) Fulfilled an organic transistor array on 4-inches quartz wafer with on/off current ratio>5x104. Established an optical and Nano-imprint systems to enhance performance and reliability of vertical polymer transistors.

I was responsible for contacting prestigious enterprises that have intention to attend an annual campus recruitment activity in NCTU.