Yuliang (Michael) Du

Sr. FPGA Engineer @ Ripple Technology Inc.

About

Sr. hardware design engineer with over 10 years of dynamic career in analog/digital design with commercial μChip/DSP components, FPGAs, proprietary ASICs, with a focus on medical devices including cochlear implant, speech processors, pacemakers and ICDs in the fast-paced class III medical industry. Functional responsibilities and competencies include: • Prototype and feasibility study for prototypes based on existing proprietary ASIC and commercial ICs. • Schematic capture through Cadence OrCAD capture, Altium design or Mentor Graphics PADS • DSP algorithm implementation and programming to TI DSP processors • Coding Atmel/Microchip embedded processors • Programming skills in VC++, C18, MATLAB and Labview • Strong background in CMOS transistor-level circuit simulation through Mentor Graphics Eldo or Cadence PSpice simulators. • Experience in designing analog/digital electronics, MCU interface, RF transceiver, power electronics • Lead the post silicon electrical characterization/failure analysis/ESD failures for ASIC blocks • Knowledge of RF impedance matching techniques and electromagnetic simulation tools. • Statistical/Cpk /trending analysis of large SQL datasets of production data with Minitab/Matlab • Generate product design specs, design requirement, verification and validation report • Initiate ECO changes through engineering/failure analysis report in product lifecycle management. • Hardware debugging skills using oscilloscope, signal generator, logic analyzer, etc. • Building ATE test equipment and design functional test coverage for cochlear implant hybrid/device test coverage • Clean room fab in 2um silicon fabrication and device characterization • Failure analysis using XIVA, FIB and SEM at die level • TLP test (HBM model) on ESD protection circuitry of the ASIC • Implement/Manage the ATE testers for medical clean room production line • Cpk control/improvement and process optimization on the implant production at wafer/hybrid level

Country

United States

City

Santa Clara

Industry

Computer Hardware

Skill

Quality System, Power Electronics Design, Electronics Hardware Design, Electronic Circuit Design, Altera FPGA, PSpice, OrCAD Capture CIS, Circuit Design, PCB Design, Semiconductors, Characterization, Signal Processing, Analog Circuit Design, R&D, Product Development, Medical Devices, Failure Analysis, VLSI, ASIC, RF

Experience

Sr. FPGA Engineer

Ripple Technology Inc.

2023-10 - Present · 3 yrs

Santa Clara, California, United States

1. FPGA top wrapper RTL development for Synopsys PCIe 3.0 IP and Cortex M7 IP integration 2. XDC constraint file generation for the HTG-840 FPGA mapping through the FMC 3. Interfacing the PCIe IP to the PHY from the third vendor 4. PCIe protocol testing with Teledyne Lecroy T34/T28 analyzer 5. JTAG/SWDIO ARM platform testing 6. Python machine learning on Ubuntu Linux

Sr. FPGA Design Engineer

Lockheed Martin

2022-11 - 2023-10 · 1 yr

Poway, California, United States

• Developed RTL for Aurora IP 100Gbit data acceleration on Xilinx U50 platform for server applications. • Implemented PCIe 3x16 lane Pair to Pair communication with NVMe to U50. • Utilized C programming for clocking and communication through QSFP link on ZCU216 platform.

Sr. FPGA Design Engineer

Microsoft

2021-11 - 2023-2 · 1 yr 4 mos

Mountain View, California, United States

• Validated RTL through FPGA emulation platform for datacenter IC on VU13P and VU19P Xilinx platforms. • Implemented and debugged PCIe IP module using PCIe protocol analyzer. • Utilized Synopsys Protosynthesis workflow for full RTL gate netlist image build.

Chief Technology Officer/Owner

Insync Biomed LLC

2021-9 - 2022-9 · 1 yr 1 mo

Santa Clara, California, United States

• Led animal study for a class III medical device at Insync Biomed LLC • Spearheaded patent application for innovative cardiac contractility device • Developed cutting-edge device with pacemaker functionality for cardiac health

Chief Executive Officer, Chairman

Advanced Robotics Corp.

2021-2 - 2021-11 · 10 mos

Los Angeles Metropolitan Area

Manages the TRL7 robotic arm development, ME design, software development, iOS app, fund raising, non-provisional patent filing at USPTO

Chief Technology Officer, Secretary

Advanced Robotics Corp.

2021-1 - 2021-1 · 1 mo

Passdena, CA

Develop the TRL3 robotic arm architecture, provisional patent filing

Staff Engineer

UBTECH Robotics

2020-6 - 2020-12 · 7 mos

Pasadena, California, United States

Electronic design of various service robots including power electronics, hand motion controller, RPi camera based detection, HRI user interface, ambient light detection, NFC verification, ROS communications of sensor messages etc

Sr. Research Engineer

Intellisense Systems, Inc.

2019-4 - 2020-6 · 1 yr 3 mos

Hawthorne, California, United States

Autonomous Drones, Xilinx FPGA code development, Matlab/simulink DSP model verification

Sr. FPGA Engineer

ThinKom Solutions, Inc.

2017-3 - 2019-4 · 2 yrs 2 mos

Hawthorne, California, United States

Schematic design of the SATCOM antenna controller, variable gain interface and RSSI boards VHDL coding of low level drivers for IMU/gyro/optical encoder/digital attenuator/ADC using Altera FPGA

Staff Engineer

Abbott

2017-1 - 2017-3 · 3 mos

Sylmar, CA

H-bridge based HV shock circuit design RF MRI measurement on Durata lead

Sr. Hardware Design Engineer

St. Jude Medical

2014-8 - 2017-1 · 2 yrs 6 mos

Sylmar, CA

ConfirmRx AFE design, full system design and integration testing, Multichannel simultaneous RF injection system design, EMI tester redesign, multi-slice SMS RF sweeping impact on the CRT-P/D devices. SBP redesign for conditional MRI compliance. Etc.