Yugesh P
DFT ENGINEER
India
Bengaluru
Semiconductors
Cadence xcelium, Synopsys Formality, Synopsys Design Compiler, Clocking, Test Cases, On chip clock control, Cascading Style Sheets (CSS), Simulation, Automatic Test Pattern Generation (ATPG), Joint Test Action Group (JTAG), Scan Insertion, EDT, Boundary Scan, Digital Electronics, Verilog
Experience
DFT ENGINEER
MSPAND Technologies Private Limited
Bengaluru
Intern
DFTTraining Institute Private Limited
Theni, Tamil Nadu, India
Education
Mepco Schlenk Engineering College
Electrical, Electronics and Communications Engineering
Yugesh P's Contact Information
Phone
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