Yu-Ting Kao
Taiwan Mandatory Military Service @ Republic of China Military Police (ROCMP)
United States
Washington DC-Baltimore Area
Computer Software
Verilog, C++, VHDL, Digital Signal Processing, Python, Field-Programmable Gate Arrays (FPGA), Machine Learning, VLSI CAD, MATLAB, Semiconductor Fabrication, Project Management
Experience
Taiwan Mandatory Military Service
Republic of China Military Police (ROCMP)
Taipei, Taipei City, Taiwan
Served as an infantryman in the Taiwanese Military Police as part of Taiwan's conscription.
Research Assistant
National Chengchi University
Taipei, Taipei City, Taiwan
Worked with Prof. Hsiu-Chuan Hsu on Quantum Computing and Digital Annealing Algorithms: • Devised mathematical objective functions and constraints based on the Ising Model • Designed algorithms to convert the modularity index into a Hamiltonian matrix • Processed complex weighted power grid graph models • Composed research papers and presented on stage at 2023 National Computer Symposium Research Papers: • “Solving Combinatorial Optimization Problems on Fujitsu Digital Annealer” Published in 2023 National Computer Symposium Conference Proceedings https://nccur.lib.nccu.edu.tw/handle/140.119/148805 • “Graph Partitioning with Fujitsu Digital Annealer”
Summer Intern
Standard Chartered
Taipei, Taipei City, Taiwan
• Worked on Mutual Fund investment and analysis. • Produced banking app tutorial video series for clients.
Student Observer
Academia Sinica, Taiwan
Taipei, Taipei City, Taiwan
• Took part in Prof. Yang-Yuan Chen's Infrared Sensing Research • Assisted with the thermal sputtering process of gold and chromium wafers • Tested the function of completed infrared sensor arrays • Presented research reports on thermoresistive micro-bridge structures.
Education
The Johns Hopkins University
Electrical and Electronics Engineering
Coursework Highlights: •FPGA Synthesis Lab: Experience with VHDL, Xilinx Cmod A7-35T, and Basys 3. Developed a standalone Flappy Bird arcade console as a course final project. • CAD Design of Digital VLSI Systems: Experience with Verilog and ASIC development with Cadence. Designed a simple RISC processor as a course final project. • Advanced Topics in Microsystem Fabrication: Fabricated a flow cytometer microfluidic chip as a course final project. Hands on experience with chip manufacturing processes in a Class 1000 cleanroom. • Random Signal Analysis: Employed various filters to predict stock market prices as a course final project. Experience with Matlab, Adaptive Filters, and Kalman Filters. • Machine Learning for Signal Processing: Introductory coursework in Machine Learning Algorithms. Employed Diffusion Models in Python for medical image generation as a course final project.
National Chengchi University
Engineering Physics/Applied Physics
(Double Major)
National Chengchi University
Finance, General
Yu-Ting Kao's Contact Information
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