Yi Fang

I am an electronics engineer currently pursuing an MSc in Electronics at Nanyang Technological University (NTU), with a background in Integrated Circuit Design and Integrated Systems. Analog & Mixed-Signal: I have hands-on experience in low-power SAR ADC design, comparator design (StrongARM latch), and analog circuit layout. I have completed transistor-level design, post-layout simulation, DRC/LVS, Monte Carlo analysis, and PVT corner verification using Cadence Virtuoso and Spectre, with a strong focus on power–performance trade-offs and silicon-level behavior. Digital Systems: On the digital side, I have designed RTL systems in Verilog/SystemVerilog, including a RISC-V CPU with pipelined architecture, covering module design, hazard handling, functional verification, and FPGA-based validation. I am familiar with digital IC design flows, simulation, and system-level debugging. AI Hardware / NPU (In Progress): I am currently working on AI hardware and NPU physical implementation, focusing on design flow automation, PPA analysis, STA debugging, and timing closure, while developing a deeper understanding of hardware-efficient machine learning and algorithm–hardware co-design. I am actively seeking internship opportunities in analog/mixed-signal IC design, digital/RTL, verification, or AI hardware, and I value collaborative teams, solid engineering practice, and continuous learning.