Yahya Hinai

• Conducting performance analysis across heterogeneous compute systems: CPU, GPU, NPU (DSP, CVP, Accelerators), memorysubsystems, and NoC interconnect. • Developed automated testing framework for comprehensive SoC analysis, focusing on CPU thread-level profiling, GPU kernel/memory benchmarking, memory subsystem characterization, and system-wide IP block efficiency report. • Evaluations of architectural proposals in cross-functional team meetings, identifying critical bottlenecks in key use cases.

• Performed system-level analysis of mobile SoC architectures, driving the design of future SoC models for Extended Reality (XR) devices & applications, with a focus on optimal performance and efficiency. • Conducting Gem5modeling of CPU architectures, Oryon (X Elite) and Kryo (XR2+Gen2), to evaluate system performance. • Optimizing computer vision algorithms on specialized hardware to meet real-time processing requirements. • Analyzing hardware/software co-design opportunities for compute-intensive workloads, targeting performance peak through design optimizations and efficient resource allocation.

1. RTL Image Recognition Accelerator Project: • FPGA-accelerated RTL engine for high-performance image processing. Covariance descriptor output reduced to (3ms) for 640x480 image input. • GPU-accelerated covariance neural network (CNN) in CUDA, establishing a performance analysis baseline performance for RTL design and HDL code generated through Vitis-HLS. 2. Complex Binary Number System (CBNS) Project: • Created RTL implementation of CBNS, a complex number arithmetic unit, achieving 4x speedup vs. conventional units. Utilized gate-level logic for base-(-1-j) full-adder. Debugging the design correctness against the standard IEEE arithmetic operations. • Simulation of CBNS Model in C++, verifying the results against golden data test cases.

1. Vortex: RISC-V Based General Purpose GPU processor | HPArch Lab at Georgia Tech | Github.com/VortexGPGPU 2. FPGA Framework for Homomorphic Encryption (HE) | SHARC Lab at Georgia Tech. 3. TinyML Design Project | Design Contest at ICCAD. 4. Circuit Partitioning: EIG+KL Hybrid Algorithm | Design Automation of VLSI Systems.

Small Satellites Project | UMN Small Satellite FPGA's Team