YAP Yi Xin

Internship in IVE - Intel Validation Engineering Memory Team 1. Participated in the Synopsys training which taught us about the introduction to IC Design and Verilog HDL, design compiler, and IC compiler II. Completed a group assignment, which requires us to build a small and efficient design by executing the DC synthesis using Design Compiler, IC Compiler II was used to complete a full cell placement, floor planning and route flow and use Prime Time to ensure the design met its timing and DRC requirements. 2. As an intern in the memory team, I grabbed the chance to try the basic techniques of validation on the hardware of the memory chip. In addition, from the task given, I learned how to use Python to create scripts to run the regression test for the cores so that failures could be found and resolved. I also got to recognize some common memory modules to be applied in the market. 3. Involved in IVE showcase, where 4 of the IVE interns presented their roles in each team, where I was from the memory team, presenting some common and unique memory modules and the learning outcomes from my team to the guests.