Yan Li
VP of Advanced Technology Group @ Sandisk
About
Expert in NAND flash memory Management * NAND Flash memory performance enhancement adaptive algorithm * NAND flash memory endurance and reliability * Advanced memory system solutions * NAND defect screen and stress * Data protection * Block management * Special NAND design features to enhance system performance and endurance Quoted by http://www.techspot.com/news/47553-sandisk-19nm-128gb-flash-memory-chip-is-worlds-smallest.html Internet Links about me https://blog.westerndigital.com/design-engineering-yan-li-from-rebel-to-innovator/ https://www.prnewswire.com/news-releases/flash-memory-summit-announces-the-superwomen-in-flash-leadership-award-winner-dr-yan-li-vice-president-western-digital-corporation-301595444.html https://www.linkedin.com/posts/western-digital_the-future-of-flash-requires-constant-innovation-activity-6770073529401569280-wqD- Dr Yan Li's whole patent portfolio summary can be found at https://idiyas.com/inventor/yan-li
United States
Milpitas
Semiconductors
Semiconductor Industry, Verilog, Engineering, Algorithms, Analog, Application-Specific Integrated Circuits (ASIC), Machine Learning, Mixed Signal
Experience
VP of Advanced Technology Group
Sandisk
Senior Director of Memory Strategy
Sandisk
Milpitas, CA
Interface with Internal and external customer Provide customized trim to customers for NAND component Provide special trim to trade off enduranace, performance, or power. Determine the die porfolia on each NAND generations to provide best cost, and best overall products Engage in new technology development
Senior Directer of Flash Memory Design
Sandisk
Milpitas, CA
* Delivered a technical talk in 2012 Flasg Summit * Presented 19nm D3 128Gb in 2012 ISSCC * Presented 56nm D3 in 2008 ISSCC * SanDisk Patent of the year in 2006 * Worked on 130nm --the first All Bitline Architecture NAND chip * Lead the design for 90nm 56nm 19nm 1Znm design team * Published 150 patents and have 30 unpublished patents
FA engineer
Sandisk
Electrical probing analog ciruits EFA, PFA FIB, SEM
VP of Engineering in Advanced Technology
WD
Milpitas, California
Taking a new position in leading NAND technology, no longer doing circuit design 3D NAND Technology Roadmap, advanced architecture and process integration, CMOS scaling 3D NAND QLC design ML committee member at ISSCC 2019 organization and team building Organize innovation events
Senior Fellow Memory Architecture
WD
951 SanDisk Drive, Milpitas, CA 95035
Senior Director Memory Architecture
WD
Milpitas, CA
Look at the memory architecture for the future 3D NAND memory development: Performance, power, Block size, IO speed. Interface with future memory controller development to bring the best performance out of SSD. Become ISSCC (International Solid State Circuit Conference) memory sub-committee member in 2017
Education
Lehigh University
Material Science and Engineering
Studied Ionic Conductivity of Ceramic materials.
University of Science and Technology of China
Yan Li's Contact Information
Phone
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