wing hin kao

Design Engineer @ ISSI Integrated Silicon Solution Inc.

About

S/DRAM Design Engineer I'm a dynamic Design Engineer with eight years of professional experience allied with a vast array of technical skills and an academic background in electrical engineering and computer science. Able to maintain responsibility for the design of a high performance and low power chip with an emphasis on micro-architectural definition, RTL coding, logic debug, timing closure, verification support, and implementation. Possessing excellent leadership and communication skills to effectively manage a group of engineers while coordinating support and instruction.

Country

United States

City

San Jose

Industry

Semiconductors

Skill

Software Architecture, Product Design, Technical Reporting, Electrical Engineering, SRAM Compiler Verification, Cadence & Synopsys Environment, Systems Engineering, Test Development, Communication Skills, C, C++, Object Orientated Java, Object Orientated Perl, Visual Basic, MIPS Assembly Language, NC-Verilog, System-Verilog, HDL, Lotus Notes, Microsoft Office, Visio

Experience

Design Engineer

ISSI Integrated Silicon Solution Inc.

2007-10 - Present · 19 yrs

Milpitas

*Responsible for the completion of a 8G/4G ECC DDR III DRAM Memory Array adn ECC/MPR/I2C function verification. *Responsible for the completion of a 72M/36M/18M QDR/DDR II/+ SRAM Memory Full Chip Design Cycle. *Exhibit full proficiency with SRAM QDR/DDR Control, Memory Array, JTAG, and Test-Mode schematics. *Implement product design and test development to facilitate multiple full lifecycles from concept to mass production. *Initiate full chip design improvements encompassing current, speed, and layout. *Account for the establishment of test strategy, test planning, and the delivery of automated test cases. *Provide expertise pertaining to scripting, full chip behavioral Verilog models, and test bench design. *Automate logic gates delay to ensure high accuracy and efficient logical verification through Object Orientated PERL-based scripting techniques. *Collaborate with design engineers to perform analysis of new technology MOSFET performance and CAD, as well as with layout engineers in relation to XRC and LVS rules files during the preliminary phase. *Liaise with Sale Group to provide technical date to customers and summarize and interpret highly technical test strategies to test and product engineers.