Vrit Raval
Formal Verification Engineer @ Google
About
Keen interest in Computer Architecture focused on Processor design, IO, NoC, Chip to Chip Interconnects. Skills: Hardware Descriptive Language: Verilog, System Verilog Hardware Verification Language: System Verilog, Methodology: FPV, UVM Concepts: Object-Oriented Programming, Randomization, Functional Coverage, FSM design, RTL coding, Layered Testbench Programming Languages: C,C++ Tools: Jasper Gold, Coverage App, Xprop
United States
San Francisco Bay Area
Computer Software
Model Checking, Test Planning, Formal Verification, Assertions, Assertion Based Verification, TCL, Perl, C, Digital Electronics, Verilog, Electronics, Object-Oriented Programming (OOP), Debugging, C (Programming Language), Microsoft Excel, Microsoft PowerPoint, Intel Quartus Prime, QuestaSim, Team Leadership, SystemVerilog
Experience
Formal Verification Engineer
Sunnyvale, CA
Google Cloud - TPU Microarchitecture, Formal Verification, Testplanning Datapath Transaction equivalence checking - C2RTL
Engineer
Arm
Austin, Texas, United States
Formal Verification
Course Grader EE 577B VLSI System Design B
University of Southern California
Los Angeles, California, United States
Grader for EE 577B under professor Moe Tabar
Engineering Computing Lab Student Worker
University of Southern California
Technical Assitant
ITS Learning Environment
University of Southern California
Technical Assistant
ASIC Design Verification Intern
NVIDIA
Westford, Massachusetts, United States
NVLINK/ PCIE Verification Methodology Intern
Design Verification Intern
Intel
Hillsboro, Oregon, United States
Compute Express Link (CXL) Team
Staff Engineer
Provino Technologies
Ahmadabad, Gujarat, India
Worked as Formal Verification Engineer.
Internship Trainee Design and Verification (VLSI)
Indicus Technology
Ahmedabad Area, India
Intensively trained on ASIC Design and Verification Skills learned: ➢RTL design through Verilog ➢Developing test plans, tests and verification infrastructure for complex IP's/sub-system ( worked on AXI Protocol VIP development) ➢Building a reusable verification environment using UVM methodology ➢Building reusable bus functional models, monitors, checkers and scoreboards ➢Writing System Verilog Assertions (SVA) to check various test scenarios. ➢Makefile and Python scripting for regression to handle multiple testcases
Education
University of Southern California
Electrical and Computer Engineering( VLSI / Computer Architecture)
Courses Enrolled: EE457 Computer System Organization (Prof. Gandhi Puvvada) 98% : Under Extraordinary group EE477L MOS VLSI Design EE557 Computer System Architecture EE577A VLSI System Design
Vishwakarma Government Engineering College
Electrical, Electronics and Communications Engineering
Recipient of Tution Fees Waiver Scheme (TFWS) by State Government which makes eligible for Zero tution fees for 4 years of Bachelor's. Relevant Coursework: ➢ Digital Electronics ➢ Digital Logic Design ➢ Electronic Devices and Circuits ➢ Analog Circuit Design ➢ Control Systems ➢ Microcontroller and Microprocessor Interfacing ➢ Data Communication and Networking ➢ Electromagnetics ➢ VLSI Technology and Design ➢ Digital Signal Processing ➢ Embedded Systems ➢ Testing and Verification
Vrit Raval's Contact Information
Phone
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