Visu Subramanian

Sr ASIC Engineer @ NVIDIA

About

Since 2010, I have primarily been involved in building software infrastructure for analyzing performance and power efficiency of GPUs. I have led various research and development design methodology efforts for optimizing GPU perf/watt. I am technically proficient in C++, Python and Perl. I have experience working on various aspects of Hardware Design. I have done RTL coding, synthesis, formal verification, timing closure, pre-silicon, and post-silicon performance and power estimation. I have experience working on CPU and GPU verification. I have worked on random program generators for CPU verification, and test generator for GPU performance verification. I have worked on performance and power modeling, as well as performance simulators. I have been a chip lead working on bringup readiness. Currently, I manage the GPU power, performance, area methodology team, as part of the Samsung Semiconductors Advanced Processor Lab. I am interested in software design methodology, data analysis, machine learning, CPU/GPU architecture and micro-architecture, performance and power efficiency analysis, low power design and features, dynamic voltage and frequency scaling, overclocking, soft errors mitigation, hardware reliability techniques.

Country

United States

City

Santa Clara

Industry

Semiconductors

Skill

Computer Architecture, Logic Design, Verilog, RTL design, Physical Design, Static Timing Analysis, Xilinx, VHDL, ASIC, TCL, FPGA, ModelSim, ARM, Algorithms, Timing Closure, Debugging, EDA

Experience

Sr ASIC Engineer

NVIDIA

2018-5 - Present · 8 yrs 5 mos

Santa Clara, CA

Sr. Staff Engineer/Manager Performance, Power, Area Architect/Methodology/Optimization

Samsung Electronics

2017-2 - 2018-5 · 1 yr 4 mos

San Jose, CA

Advanced Computing Lab (ACL)/Samsung Austin Research Center (SARC) within Samsung LSI group. Responsible for GPU performance and power modeling and estimation infrastructure. Also, worked on GPU performance optimization and POR configuration architectural studies. Responsibilities include: Light weight simulator for performance/watt estimation/projection. Simulation and emulation power and performance estimation methodology. Performance and energy modeling and correlation. Unit level and GPU top regression infrastructure. PPA metrics reporting and tracking. Improve energy efficiency of light-workload use cases. Perf/W optimization solutions. Unit/fullchip GPU Performance verification. Unit/fullchip GPU Power verification.

Sr. Staff Engineer 2

Samsung Electronics

2015-6 - 2017-1 · 1 yr 8 mos

Mountain View, CA

GPU power, performance, area methodology, infrastructure and toolchain devlopment lead in the Advanced Processor Lab.

Sr. ASIC Design Engineer

NVIDIA

2009-8 - 2015-6 · 5 yrs 11 mos

Santa Clara, CA

- Technical lead for pre-silicon power estimation methodologies based on RTL simulation and emulation.

Reserach Assistant

Iowa State University

2006-5 - 2009-7 · 3 yrs 3 mos

Ames, IA

Fault Tolerant Architectures: Implemented a novel fault masking methodology to protect microprocessor control logic. The implementation was done in OpenRISC 1200 from Open-Cores.org. Developed a novel conjoined pipeline architecture based on organized pipeline redundancy to enhance microprocessor dependability and performance. Designed and developed register cells that mitigate soft errors, as well as, support reliable overclocking. Reliable Overclocking to Achieve High Performance in Superscalar Processors. Worked on timing error detection and correction in overclocked superscalar processors. Analyzed a hardware model of an alpha processor to estimate error rates at overclocked frequencies. Modified SimpleScalar Toolset to analyze performance benefits achieved through reliable overclocking. Developed a dynamic clock tuning methodology using phase locked loops available in Xilinx Virtex 5 FPGAs. Developed tool set for DLX processor DLX GCC Compiler and DLX Assembler. Analyzed the benefits of reliable overclocking in a 2-issue superscalar DLX processor implemented in FPGA Thermal Aware Microprocessor Design Developing novel architecture based on DVFS and reliable overclocking to manage temperature and performance of microprocessors.