Vishal R.

Vishal R.

ASIC Engineer, Physical Design @ Meta

About

Vishal Raghuvanshi is a motivated Physical Design Engineer with 5+ years of hands-on experience in High-speed Custom SoC Designs across advanced technology nodes (7nm, 5nm, 3nm). Skilled in RTL2GDS and signoff aspects of ASIC backend design, including synthesis, PnR, EMIR, LEC, physical verification, power analysis, and LPV. Proficient in tools like Synopsys (Fusion Compiler, PrimeTime, PrimePower, PrimeClosure, StarRC, Formality, VCLP, Verdi, Design Compiler, Redhawk, DSO.ai, DesignDash); Cadence (Encounter, Virutoso, Innovus, Voltus, Conformal, Genus); Xilinx (ISE, Vivado), Mentor Graphic Calibre, Ansys HFSS.

Country

United States

City

Austin

Industry

Computer Software

Skill

Static Timing Analysis, Physical Design, Very-Large-Scale Integration (VLSI), System on a Chip (SoC), Application-Specific Integrated Circuits (ASIC), Integrated Circuits (IC), Circuit Design, Shell Scripting, C (Programming Language), Microsoft Office, Matlab, Verilog, Python (Programming Language), Simulink, ANSYS HFSS , Perl, Public Speaking, University Teaching, Synopsys Primetime, Cadence Virtuoso

Experience

Meta

ASIC Engineer, Physical Design

Meta

LinkedIn
2025-6 - Present · 1 yr 4 mos

Austin, Texas, United States

Microsoft

Physical Design Engineer II

Microsoft

LinkedIn
2022-8 - 2025-5 · 2 yrs 10 mos

Morrisville, North Carolina, United States

Microsoft

Physical Design Engineer

Microsoft

LinkedIn
2020-6 - 2022-9 · 2 yrs 4 mos

United States

Samsung Semiconductor

CPU Physical Implementation Intern

Samsung Semiconductor

LinkedIn
2019-6 - 2020-1 · 8 mos

Austin, Texas Area

• Contributed to the design and optimization of a 5nm CPU and memory subsystem, focusing on performance and power efficiency. • Led multi-scenario timing closure, signoff, and ECO flows across various CPU blocks to ensure robust functionality and timing accuracy. • Gained hands-on experience in Static Timing Analysis (STA), including core timing analysis & reporting, graph-based & path-based analysis, SI-crosstalk, and OCV analysis, while assisting in timing feedback creation and constraint validation. • Addressed DRC violations related to max capacitance, max transition, noise, and timing violations (setup & hold) through effective debugging and resolution strategies. • Automated repetitive tasks such as violation analysis and report generation by creating TCL scripts, improving workflow efficiency. • Performed timing correlation between physical implementation (IC Compiler-II) and golden signoff (PrimeTime), identifying and resolving miscorrelation issues by analyzing tool databases. • Developed a TCL script to identify and report bad pin placements at both top-level and hierarchical sub-tiles, enhancing design accuracy. • Worked on power analysis for Clock Tree Synthesis (CTS) and optimization, ensuring power efficiency in high-performance CPU designs. • Monitored weekly power build runs for the 5nm GPU design, tracking design changes and identifying discrepancies to ensure optimal power performance.

ISRO - Indian Space Research Organisation

Junior Research Fellow

ISRO - Indian Space Research Organisation

LinkedIn
2017-1 - 2018-4 · 1 yr 4 mos

Hyderabad, Telangana

•Worked as a part of Radio Frequency Baseband Division Team at National Remote Sensing Centre, Hyderabad, India. •Designed and simulated a conformal X-Band dielectric rod antenna (DRA) with an operational frequency of 8.25 GHz using high-frequency structural simulator (HFSS). •Analyzed the effects of mutual coupling in DRA arrays by simulating at different scan angles. •Conducted a study on metamaterials as a decoupling network and realized them using double split-ring resonators (SRRs) using Ansoft HFSS and MATLAB. •Investigated magnetic resonance of SRRs experimentally and numerically along with the dependence of their geometric parameters on the resonance frequency of SRRs. •Simulated large number of SRR arrays between DRA elements showed a significant reduction in mutual coupling. •Thesis on project title “Electromagnetic Coupling Reduction in Dielectric Rod Antenna Array using Single Negative Magnetic Metamaterial” successfully completed and submitted to NRSC.

Education

Texas A&M University

Texas A&M University

LinkedIn

Electrical and Computer Engineering

2018 - 2020 · 2 yrs

Recieved Graduate Merit Scholarship Award from the Department of Electrical and Computer Engineering.

University Institute of Technology, RGPV

University Institute of Technology, RGPV

LinkedIn

Electronics and Communications Engineering

2012 - 2016 · 4 yrs

Vishal R.'s Contact Information

Email

******@***.com

Phone

(**) *** ****

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