Vineet Rathish

Senior Design Verification Engineer @ Qualcomm

About

I recently graduated with a Master’s degree in Electrical Engineering from San José State University, specializing in Digital Design and Verification. My academic journey and hands-on project experience have equipped me with a strong foundation in front-end VLSI design, RTL implementation, and ASIC/FPGA verification methodologies. I am passionate about building robust, scalable, and efficient digital systems. My core competencies lie in Verilog, SystemVerilog, and UVM, and I’m actively seeking opportunities in Front-End Digital Design and Verification roles including: > RTL Design Engineer > ASIC/SOC Design Engineer > Design/ASIC Verification Engineer > FPGA Verification Engineer > CPU/GPU/SOC Verification Engineer Technical Proficiencies > HDLs/HVLs: Verilog, SystemVerilog, UVM > Verification Methodologies: UVM, Constrained Random Testing, Assertions, Coverage-Driven Verification, Scalable Testbench Design > Programming: C, C++, Python > Scripting: Python > Protocols: AMBA AXI4, APB, AHB, I2C, SPI, UART, PCIe, DDR > Design Concepts: FSMs, RTL Design & Synthesis, STA, CDC, MIPS Pipeline, Cache Coherency I bring a combination of strong debugging skills, methodical verification strategies, and a deep understanding of digital logic fundamentals. I’m committed to continuous learning and excited to contribute to innovative and high-impact silicon development teams.

Country

United States

City

San Jose

Industry

Semiconductors

Skill

Verification, System on a Chip (SoC), Assembly Language, Orthogonal Frequency-Division Multiplexing (OFDM), Image Processing, Cache Coherency, CPU design, MIPS Instruction Set, Simulink, Digital Signal Processors, Signal Processing, Universal Verification Methodology (UVM), RTL Verification, Functional Verification, Hardware, Analog Circuits, Opamp, NumPy, Pandas, VLSI

Experience

Senior Design Verification Engineer

Qualcomm

2026-2 - Present · 8 mos

Santa Clara, California, United States

Instructional Student Assistant

San José State University

2024-9 - Present · 2 yrs 1 mo

San Jose, California, United States

As an Instructional Student Assistant for EE112: Signal Processing at San José State University, I guide students through signal processing projects, offering step-by-step support in tasks such as Filtering, Fourier transforms, and signal analysis. I also develop and grade assignments to ensure students grasp key digital signal processing (DSP) techniques. Additionally, I lead lab sessions and tutorials where students implement signal processing algorithms in Verilog and MATLAB helping them bridge the gap between theoretical concepts and practical applications.

Research Assistant

San José State University

2025-7 - 2026-1 · 7 mos

San Jose, California, United States

Software Engineer

LTIMindtree

2021-9 - 2023-8 · 2 yrs

Mumbai, Maharashtra, India

Developed and optimized customer-facing and internal web products using JavaScript at SBI Life Insurance by collaborating with cross-functional teams to automate key processes and streamline frontend and backend operations, reducing system downtime by 25% enhancing user experience. Automated key modules like Maturity, Annuity, Survival Benefit, Surrender, by debugging and resolving high-priority production issues. Led deployment, testing, documentation, and coordinated frontend and backend integrations

Graduate Engineering Trainee

LTIMindtree

2021-6 - 2021-9 · 4 mos

Mumbai, Maharashtra, India

- Completed training one several tools and technologies like Springboot, SQL, Hibernate, and Agile Development as well as Full Stack Development using Java and Python. - Designed and Programmed an employee grievance portal along with a team of 5+ individuals, in a remarkable span of 3 weeks - Led a batch of over 60+ new joinees as the Batch Representative of JAVA Full Stack Batch

FPGA Design Assistant

University of Mumbai

2020-6 - 2021-6 · 1 yr 1 mo

Mumbai, Maharashtra, India

Led a research-based project to design a highly efficient Pseudo Random Binary Sequence (PRBS) using oscillators and Chaotic Logistic Maps, optimizing performance for FPGA-based systems and improving efficiency by 20%. Developed python scripts to generate the PRBS and integrated them into FPGA workflow via MATLAB Simulink. Implemented the design on the PYNQ FPGA board using Xilinx Vivado. Validated and verified the PRBS, passing all performance benchmarks in the NIST Test Suite, with precision values from 5-256 bits, achieving high product throughput, making it ideal for applications ranging from gaming to cryptography.