Vinay Sreedhara
Silicon Engineer @ Meta
About
6+ Years of professional experience in the VLSI industry delivering high quality results for companies like Google, Meta(Reality labs) and Intel in the Department of Physical Design and Verification.Expertise :: Standard Cell Schematic and layout automation, RTL Design, Synthesis, Physical Design tasks such as Floorplanning, Power Planning, Placement, CTS, STA, EM-IR, PPA-Optimization, Physical Verification(DRC, LVS, DFM, Antenna, Density, PERC), Runset Dev Validation (LVS, ERC), Current Density Analysis and Fixing, Computer Aided-Design(CAD).Design Interests :: Microprocessor System Design, CPU, GPU, DDR, DPU Tools :: DC/DCT(dc_shell), Genus, Fusion Compiler(FC), IC Compiler(ICC), Innovus, PrimeTime(PT/PTSI), Tempus, VCLP, Conformal, IC Validator(ICV), IC Validator WorkBench(ICVWB), Calibre, CalibreDRV, Cadence Virtuoso, Voltus, QuestaSimNodes worked on :: 14A, 18A(Intel), 3ne, 4nm(TSMC), 5nm(Samsung), 7nm(Intel), 10nm(Intel), 14nm(Intel).Scripting/Coding Skills :: Unix, System Verilog, Verilog, TCL, Shell, Python.
United States
Austin
Semiconductors
Clocking, Clock, Engineering Change Order, EDA, Application Programming Interfaces (API), Signal Integrity, Noise, Cross-Talk, CTS Algorithms, PPA, Written Communication, Problem Solving, High Performance Computing (HPC), Computer Science, Antenna Violation, Progressive Discipline, Digital Circuit Design, MCMM, ECO, Object-Oriented Programming (OOP)
Experience
Silicon Engineer
Meta
Austin, Texas, United States
Member of Technical Staff
Rivos Inc.
Austin, Texas, United States
Graduate Technical Intern
Intel
Hillsboro, Oregon, United States
Design Engineer (Clients :: Meta and Google)
Eximius Design
• Completed a MOCK-TO with Google, managing various responsibilities of Physical Design and Verification for a DPU in 4nm TSMC technology. • Achieved sign-off closure for multiple GPU/CPU Blocks with diverse challenges like timing criticality, EM-IR restrictions, and high-level routing congestion scenarios. Contributed to Automation of systematic DRC and LVS closure(Block-Level/SoC Level) in 5nm Samsung Technology for an in-house project for Facebook (Meta Labs).
Physical Design Engineer(Sevitech Systems)
Intel
Been part of Intel(HPG, C2DG, Big Core), Have been part of 8 Tape-Ins and 1 Tape-Out in DSM Nodes like 7nm, 10nm and 14nm.
Physical Verification Intern(Sevitech Systems)
Intel
Worked as Layout Verification Engineer at Intel on serveral Projects handling responsibilities of a Physical Verification Sign-Off items like DRC, LVS, ERC, DFM etc.
Physical Design
RV Skills Design Centre
Completed an RTL2GDS Project for an 833Mhz design with 45 IPs designing and implementing each and every step of Physical Design Flow to achieve the best possible PPA with DRC/LVS Clean GDS.
Standard Cell Design
Vivartan Technologies
Designing high density standard cell Library in technologies like 45nm,90nm and 180nm
Education
Portland State University
Vidyavardhaka College of Engineering
Electrical, Electronics and Communications Engineering
NIIT Institute
Programming in C
NIIT Institute
Object Oriented Programming using C++
Vinay Sreedhara's Contact Information
Phone
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