Vijay Kodithyala

Si DE Manager @ Intel

About

Demonstrated leader in CPU design team with a passion for physical design for Si & 3DIC. SKILLS: 1. Deep understanding of Technology in Si-Processing and Assembly, PDK/PADK collaterals and standards, EDA tools & capabilities, Product design methodology and design lifecycles, milestone needs & quality expectations through tape-outs. Expertise in environment support with PDK/PADK collaterals for multiple chip-let design and assembly 2. Lean methods, Customer first attitude, Broad technical skills in Process technology collaterals and EDA tools. Expertise in Design automation, SoC integration, IP Quality and delivery, product integration. 3. Physical design implementation spanning custom/APR design/convergence, DRC/LVS, extraction and reliability through full chip design and tape-out. Expertise in SoC integration, full chip design completion, verification and tape-out signoff. 4. Recent study of RiscV architecture, Hardening IP for it on Sky130A. Learning PyTorch/AI training for ImageProcessing. Design Automation Principal Engineer: Enabled key design flow capabilities on cutting edge Intel Technologies in custom, analog, Place & Route blocks and delivered over a dozen CPU tape-outs, with core in-depth skills in physical design, physical verification and tape-out signoff.

Country

United States

City

Portland

Industry

Semiconductors

Skill

Integrated Circuits (IC), Layout Design, Circuit Design, VLSI CAD, Very-Large-Scale Integration (VLSI), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Physical Verification, Semiconductor Engineering, Design Automation, 3DIC, Packaging Design, fullchip, Product Design, Bridge Technology improvements to EDA design flows to lower cost for the entire ecosystem for Intel Technology, 3DIC support and packaging enablement in Intel Kits, Design Methodology and Automation for Ease Of Use with Intel Kits, EDA, Analog, Processors

Experience

Si DE Manager

Intel

2026-1 - Present · 9 mos

North America

Designing leading interconnect Si on latest Intel tech for Interposers and Embedded Bridges, enabling 3DIC chips that fuel the latest Compute and AI growth.

PDK ADK Manager

IBM

2025-6 - 2025-12 · 7 mos

North America

PDK & ADK manager in Design Enablement team, IBM Semiconductor Technology Research and Development. Conducting Research and Development of leading technology such as 2nm & 1.4nm as well as for 2.5D and 3D Assembly technologies. We support development of specialized process flavors for unique products.

Principal Engineer, PDK Architecture, Intel

Intel

2012-1 - 2024-11 · 12 yrs 11 mos

Analyze technology updates and their impact to PDK, P&R/Custom techffiles, RC extraction techfiles etc and work with EDA tools, flows, automation to ensure ease-of-use and rapid adoption in design community. Established standards and improved PDK dev&QA throughout. Standardized IP Quality requirement and reduced effort for integration into SoC. Defined multi-domain power delivery grids required for large IPs such as DDR and enabled automation for design completion in Analog and digital circuits.

Principal Engineer, IAG, Intel

Intel

1995-10 - 2012-1 · 16 yrs 4 mos

Hillsboro, OR

Owned design methodology with a focus in Physical design for analog, digital, block-level, HIPs, Fullchips and SoC designs. Depth in design methodologies in Physical design (Virtuoso), PDNs, Physical verifications (ICV/Hercules), RC extraction(StarRCXT), EM/IR helped drive efficiency across multiple microprocessor product delivery. Innovated and delivered many key capabilities on cutting edge technologies at Intel for over a decade. Achieved many 'firsts' at Intel... automated and streamlined designs for new Lithography impacts, enabled physical design migration, rapid resizing to enable fast ECOs, constraints based analog topological layout generations. Defined requirements and enabled new flows and methodology on lead products for each new technology, proliferated to and trained other design teams at Intel for follow-on products. Drove integration of blocks/IP into fullchip to physical verification signoff and tapeout for over a dozen microprocessor products.