Veeranjaneyulu Dhikonda

Handling DFT architecture, DFT execution and Methodolgies for hierarchical and flat designs End -to End implementation

Led retargeting of SSN (Scan Streaming Network) architecture from core-level to full-chip integration across multiple cores, including complex IPs such as HBM, PHY, and PCIe subsystems, ensuring scalable and efficient hierarchical DFT implementation. Enabled seamless reuse of core-level ATPG patterns at chip level by developing robust retargeting methodologies, significantly reducing pattern generation time and improving productivity. Integrated and validated DFT for high-speed interface blocks including HBM (High Bandwidth Memory) controllers PHY layers (SerDes/IO interfaces) PCIe (Peripheral Component Interconnect Express) subsystems while addressing domain-specific challenges such as clocking, power modes, and protocol constraints. Optimized SSN bandwidth and scan distribution across heterogeneous cores and interface IPs, ensuring efficient parallel test execution and reduced overall test time. Debugged and resolved complex issues related to scan chain stitching, compression compatibility, X-propagation, and test access limitations across HBM/PHY/PCIe blocks during chip-level retargeting. Collaborated with IP, design, and physical design teams to ensure DFT alignment across diverse blocks, enabling robust integration and smooth silicon bring-up. Ensured coverage consistency and high test quality across core-level and chip-level implementations, even with mixed architectures and high-speed interfaces.

End-to-End DFT plan, strategies and execution from pre and post silicon support using EDA tools at soc and core level (Bscan, MBIST, Scan, ATPG and Simulation as well as post silicon debugging)

DFT-RTL designer, ECO implementation at RTL level, FEV checks, Implementation on TR phase, CDC checks at partition and soc.

Currently, I am working as a contract worker in maxim integrated limited through Anora semiconductor pvt.ltd for 1 year till the date. My Roles and Responsibilities:- ATPG, simulations and DFT test point insertion at digital top level & chip top level by using Synopsys Tools. Problematic handling timing and no-timing simulations in NCsim tool.Coverage improvement technics followed by the flow. Adding dummy cycle in SPF, manual edits compression logic SPF at wrapper level.Diagnosis experience for IDDQ in mentor and Synopsys tool. Analyse assumed test points by using the Synopsys tool. Masking the scan flip-flops or non-scan flip-flops based on the STA reports.

Well Known About Scan Insertion And JTAG Topics:- ASIC Flow, DFT fundamentals, SCAN Design, SCAN DRC, SCAN Insertion, Scan Compression, Boundary Scan, JTAG, ATPG Faults, Fault models, ATPG Coverage, ATPG for Stuck-at and Transition fault models and Pattern simulations. Well Known about tools-Synopsys -DFT Compiler, Cadence Genus(Scan Insertion), ATPG -Tetramax, ET Test, JTAG -BSD Compiler, Simulation - VCS, NCS Simulation. I worked Dig-top, Falcon projects in Synopsys tools Custom test data register to control entire logic given DTMF Chip with User defined instruction by using JTAG insertion in the tool. adding cut points to the particular TDR output pins in sequence file, writing a tap controller program based on TDI input of custom TDR register in the sequence def file. Well Knowledge in MBIST, LBIST, and IJTAG., Hands-on experience in Python Scripting