Veena munnurukapu

DDR/LPDDR Protocol Training @ Vlsiguru-Hyderabad

About

I am a Hardware Design and Verification Engineer and an M.S. Electrical Engineering candidate at San Jose State University. My expertise lies in High-Speed Memory Controllers, SoC Architecture, and Advanced Verification Methodologies. With a background spanning RTL design, UVM verification, and post-silicon validation, I specialize in ensuring data integrity for next-generation silicon. ### Specialized Expertise in Memory Subsystems My technical core is rooted in DDR3/DDR4 and LPDDR protocol architecture. I have designed AXI-to-DDR3 memory controller front-end RTL, incorporating JEDEC command scheduling and arbitration logic. I am proficient in:Initialization & Power-up: Managing reset sequencing and state machine transitions for DDR/LPDDR.Training & Calibration: Validating Write Leveling, Read Training, CA Training, and ZQ Calibration.Interface Standards: Utilizing DFI (DDR PHY Interface) to decouple controller logic from the physical layer for 1GHz+ deployments. ### Robust Design & Verification Capabilities I leverage SystemVerilog and UVM to build scalable, high-coverage verification environments. My portfolio includes:RTL Design: Architecting 5-stage pipelined RISC-V CPUs, Out-of-Order Tomasulo processors, and AI Calculation Engines.Verification Mastery: Developing UVM testbenches with constrained-random stimulus, functional coverage, and SVA.Timing & Sign-off: Achieving timing closure using Synopsys PrimeTime STA and performing power analysis for 12nm SoC components. ### System Validation & Performance ModelingValidation: Using oscilloscopes and protocol analyzers to root-cause signal integrity issues in Ethernet and DDR controllers.Modeling: Utilizing Gem5 (C++) and Python to model SoC hierarchies and evaluate bandwidth/latency trade-offs. ### Technical ToolkitLanguages: SystemVerilog, Verilog, VHDL, C/C++, Python, Tcl, Shell. Protocols: AXI4, AXI-Lite, APB, DDR3/DDR4, LPDDR, I2C. EDA Tools: Synopsys VCS, Design Compiler, PrimeTime, Cadence Virtuoso, Spectre, ModelSim, Vivado. I am passionate about pushing the boundaries of memory-level parallelism and low-power SoC design. Let’s connect!

Country

United States

City

San Jose

Industry

Semiconductors

Skill

C++, Process Automation, Data Analysis & Debugging, Workflow Optimization, System Performance Analysis, Cloud Computing, MATLAB, yolo v7, Phase Noise, TCL, Technology Education, Test Scripts, Information and Communications Technology (ICT), Analog Integrated Circuit Design, Process Analysis, Device Design, Stability Testing, Memory Test, System Configuration, HIL

Experience

DDR/LPDDR Protocol Training

Vlsiguru-Hyderabad

2025-12 - 2026-3 · 4 mos

Memory Architecture: Deep understanding of DDR/LPDDR memory organization, pinout configurations, and Controller/PHY architecture within SoC integration. Protocol Mastery: Expert knowledge of memory commands, timing diagrams, Mode Register (MR) configurations, and clock frequency constraints. Initialization & Calibration: Proficient in the complete power-up sequence and critical training procedures, including Write Leveling, Read Training, CA Training, and ZQ Calibration. System Integration: Studied SoC-to-Memory interfacing, focusing on signal integrity and timing closures required for high-speed data transfer.

Internship Trainee: Advanced Digital Design Verification

lucid vlsi

2024-5 - 2024-7 · 3 mos

Project: End-to-End Verification of Router 1x1 DUT Developed a complete class-based verification environment from specification, transitioning from basic Verilog to advanced SystemVerilog (SV) constructs to ensure modularity, scalability, and high verification confidence. ### Testbench Architecture & OOP Hierarchical Environment: Designed a modular SV testbench consisting of a Top-level module, Interface, and Program Block. Component Development: Built a structured Environment Class encapsulating the Generator, Driver, Input/Output Monitors, and Scoreboard for comprehensive DUT verification. Class-Based Design: Migrated from module-based to OOP-based architecture, utilizing transaction classes and constructors to improve testbench flexibility and reusability. ### Stimulus & Communication Constrained Randomization: Implemented randomized stimulus generation with user-defined constraints to automate corner-case discovery and maximize functional reach. Mailbox Communication: Utilized Mailboxes and event triggers for seamless inter-component communication, ensuring synchronized data flow between the Generator and Driver. ### Synchronization & Abstraction Interfaces & Clocking Blocks: Integrated Interfaces with Clocking Blocks and Modports to ensure race-free signal sampling and driving, significantly enhancing timing accuracy. Program Blocks: Used Program Blocks to isolate testbench execution from hardware simulation, preventing sampling errors and improving abstraction. ### Coverage & Quality Assurance Functional Coverage (FC): Developed Covergroups with custom bins and Cross-Coverage to measure stimulus completeness and validate that all design requirements were met. Self-Checking Scoreboard: Built a robust scoreboard to automate data integrity checks, comparing input packets against output results for real-time pass/fail validation. Technical Stack: SystemVerilog, Verilog, OOP, Constrained Random Testing (CRT), Functional Coverage, RTL Verification.

Data Analyst

All India Council for Technical Education (AICTE)

2022-9 - 2023-5 · 9 mos

• Completed a 9 months AWS-supported program in data analytics and cloud workflows. • Applied Python, SQL, and visualization techniques to derive data-driven insights. • Strengthened automation and analysis skills for verification regression and SoC performance modeling.

Salesforce Developer

SmartInternz

2022-4 - 2022-9 · 6 mos

Hyderabad, Telangana, India

• Developed and debugged Salesforce applications utilizing Apex, LWC, and API integrations with VS Code & CLI setup. • Completed Superbadges in Apex Specialist and Process Automation Specialist, showcasing advanced automation skills. • Enhanced software engineering and scripting capabilities, contributing to UVM automation and HW/SW co-validation in engineering roles.

Process Mining

Celonis

2022-1 - 2022-4 · 4 mos

• Gained hands-on experience with process mining tools and data-driven workflow optimization using Celonis software. • Analyzed system bottlenecks and inefficiencies to identify automation opportunities through real-world case studies. • Strengthened skills in data analysis and debugging process flows, enhancing verification coverage and regression analysis.