Varun Saxena

GTA for the CS 3220: Processor Design course under Prof. Hyesoon Kim for Spring 2023.

Project lead working on ideation, architecture, microarchitecture and design for vector engine extension of the GPGPU (Vortex) in HPArch Lab. Optimizing for power-perf-area and provided customization for vectorization levels between cluster and core. Led a team of research students.

Developed a design-aware stimulus generation block for a unit in the graphics pipeline to generate better stimulus for different graphics components in the block to target "more interesting" cases in lesser seeds.

Topic: Rasterization engine for Graphics Acceleration on GPGPU in RTL (https://vortex.cc.gatech.edu/) Advisor: Prof. Hyesoon Kim Micro-architected, designed (in RTL) and integrated a rasterization engine into the Vortex GPGPU (https://vortex.cc.gatech.edu/) for graphics rending. The engine used a 2 phase recursive descent approach. It used optimized data ordering from the host-CPU and accessed the data from the DRAM using a finite state machine and storing the run-configurations in reservation stations. This acts as a load balanced to distribute the run-configurations into different rasterization slices for evaluations. The slice then recursive evaluates and divides the tiles till it becomes small enough for parallel quad evaluations (block size). The block is then dispatched to a block evaluator to evaluate the quads in parallel. The quads are then pushed into a quad FIFO via an arbitration mechanism. The output crossbar then dispatches the available quads from different slices to the requesting cores. Various design optimizations were applied to reduce area, critical path and enhance functionality. It was tested using different tile configurations, core count, slice count, etc. using the PowerVR SDK image samples. Publications: 1. Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs, ASPLOS'23 2. Accelerating Graphic Rendering on Programmable RISC-V GPUs, 2022 IEEE Hot Chips 34 Symposium (HCS)

Owned, created, and developed various tools and methodologies for Analog and Digital circuit design and verification. Worked on the following tools: ● Memory Compiler Tool: Created DesignSync interface-based memory version history generation, optimized the memory release runtime (90%), integrated the fixed-IP generation flow into the compiler, added/updated various generators, created a centralized auto-sync mechanism for memory data between compiler and dependent utilities, etc. ● Electrostatic Discharge (ESD) Verification Tool: Ideated and developed new features and flow optimizations to improve efficiency (~3x) in TI’s configurable simulation based ESD verification framework in Cadence Virtuoso. Added new flows for auto-reconfiguration of the design environment, concurrent multi-stress simulation setup, auto-upgrade of environment to latest Cadence ADE Assembler setups, etc. ● ESD Sign-off Tool: Led the development of GUI based tool from ground-up for configuring and generating the statistical ESD sign-off reports by processing results from different ESD verification flows. ● Cell-to-Design ESD Review propagation: Created framework from ground-up to standardize ESD verification runs for IO-libraries and auto-import manual ESD reviews from IO-cells to DUT with >95% accuracy. ● Analog Mixed Signal (AMS) verification Tool: Developed new features for TI’s AMS Design Verification regression framework to optimize LSF runs, replay capability for post-processing checkers, added plugins for flow control, etc. ● Other projects include work on SoC configuration tool, Magillem based IP-XACT interface development, database for verification and validation metrics, etc.  Created test regressions (GUI + command line) with auto-run and notification for the above tools.  Assigned project leadership for memory publishing flow and AMS verification tool. Project owner for ESD Sign-off tool since conception.

Worked on automating the process of static and dynamic parameter (Component Area Voltage) extraction from the design schematics, netlists and design hierarchy XMLs. This data was then processed, modified and formatted in SQLites readable by other in-house tools. For this project, I had to study various design hierarchy dependencies, hierarchy data generation, netlist parsing, design database structures and different simulations flows. Further on, I used Cadence SKILL language to integrate the tool into Cadence Virtuoso. On completion of the internship, I received a Pre Placement offer for full time job at TI.

Responsible for organizing all the electronics related activities for IEEE-NSIT section. I was a part of the core organizing team for the IEEE AICSSYC’15 congress, IEEE-NSIT Hardware Hackathon’16-17 and various electronics and robotics competitions. Ideated and taught in the "Art of Electronics" SIG(special interest group) classes.

Responsible for organizing the events by IEEE-NSIT section as a part of the event management team.

Worked on Motion Estimation using optical flow mechanism on MATLAB as a part of winter training in college. Generated motion vectors to represent the direction and speed of an object in a video using Zernike, Horn schunck and Lucas kanade algorithms.

I was 1 among 30 students selected from all over India for this training. I was trained by industry experts in the field of CMOS Analog IC design and worked on a design two stage Op-amp project to meet target specifications.

Concentration: Digital VLSI and Computer Architecture Fall 2021: Advanced VLSI Systems Advanced Computer Architecture Digital System Testing Advanced Programming Techniques Spring 2022: FPGA Accelerators Interconnections Networks for High Performance Special Problem on Graphics Acceleration on GPGPU (under Prof. Hyesoon Kim) Technology Entrepreneurship Spring 2023: Special Problem on Vector Engine in GPGPU (under Prof. Hyesoon Kim) Quantum Computing Devices and Hardware Global Entrepreneurship

Standing: First Class with distinction Bachelor Thesis Project: Power and Area aware automated transistor sizing of CMOS logic circuits using Logical Effort theory and Cuckoo Search Algorithm Relevant Courses Completed: Electronics 1 & 2, Circuits and Systems, Digital Circuits and Systems 1 & 2, Computer System Organization, Linear Integrated Circuits, Microprocessors, Bipolar & MOS Analog Int. Circuits., Filter Design, Switching Automata, Introduction to VLSI