Vandit Mehra

- Performance modelling and architecture simulation of state-of-the-art graphics pipeline (GPU) architecture. - Model development and performance triage of architecture specification for next-gen graphics processors in early stages of projects using in-house proprietary simulator. - Identifying architecture, micro-architecture, and implementation optimizations to improve performance, power, and area of the GPU and its units - Simulate OpenGLES and Vulcan graphics benchmarks and in-house benchmark suites, analyze and report resultant performance data to enable future performance enhancements to the GPU pipeline. - Work closely with the RTL design teams to understand the architecture and micro-architecture of the GPU and its units and to triage and fix performance related issues

Architecture Simulation and performance modelling of state-of-the-art graphics pipeline (GPU) architecture. - Develop a bit-accurate performance model of architecture specification for next-gen graphics processors in early stages of projects, focusing on shader/execution/arithmetic core pipeline. - Simulate GLES graphics benchmarks and in-house performance verification suites on the model and analyze and report resultant performance data to drive feature addition/improvement for future products.

• Working closely with the RTL design teams to understand the architecture and micro-architecture of the GPU and its units and to triage and fix performance related issues • Develop tools and methodology to correlate and validate performance model against RTL design and Spec • Identifying architecture, micro-architecture, and implementation optimizations to improve performance, power, and area of the GPU and its units • Develop and execute performance test plans on GPU and units level

Responsibilities include - Verification of low-power SoC power grid extraction engine exhaustively. - Developing test-cases in Verilog & LEF-DEF formats verifying desired functionality for power-ground rail extraction aiding low power chip design and employing logic simulators to generate inputs for the extraction engine. - Running Logic Simulation and employing Design Automation and scripting (TCL, Perl, Python and c-shell) to automate the verification process.

Underwent intensive training in Global System for Mobile Communication(GSM), Base Transceiver Station Site Development and Internet Protocol based Television (IPTV) Transmission.

Developed Touch Sensor controlled robotic vehicle using advanced microcontrollers Implemented Embedded C programming for developing automation modules