Vahid Lari

Program Manager – Parameter Handling - Lead three international workstreams covering front-end, back-end, and stakeholder deployment, delivering a unified software platform for parameter and data handling across complex engineering programs. - Directed milestone and budget planning to ensure on-time delivery and alignment between technical teams and strategic business goals. - Scaled stakeholder engagement from five to more than fifteen internal customers across global programs by presenting the platform’s value to project leads and senior management, driving widespread adoption. - Expanded and led a distributed team of 15–20 developers across multiple locations, strengthening collaboration and delivery efficiency. - Implemented a structured release strategy that transformed release predictability, reducing frontend delivery cycles from two per year to every six weeks and synchronizing backend releases accordingly. - Achieved major efficiency gains, cutting deployment effort from about one month to less than one week, reducing parameter change times from one day to under ten minutes, and optimizing backend code generation from minutes to seconds. - Drove platform adoption across multiple business units by demonstrating measurable ROI through faster updates, consistent release quality, and improved stakeholder trust. Key Achievements: - Achieved a 3× increase in release frequency and improved predictability across releases - Reduced platform rollout effort by more than 80% - Expanded platform adoption more than 3× across Bosch engineering programs

Platform Parameter Handling Backend Tool - Owned and drove the development of a backend code generation platform supporting parameter and data handling across multiple engineering programs. - Provided technical leadership and oversight of roadmap definition, sprint management, and team coordination to align feature delivery with stakeholder priorities. - Expanded the team from one engineer to over seven, establishing agile delivery processes and clear ownership structures that improved development efficiency. - Partnered closely with cross-functional teams to ensure the platform’s scalability and integration into existing toolchains. - Scaled stakeholder adoption from a single pilot customer in 2021 to more than five active users by the end of 2022, demonstrating strong internal traction and value creation. - Contributed to the business success of the pilot project by reducing overall memory consumption by 15%, resulting in improved system performance and stability. Key Achievements: - Scaled stakeholder base from 1 to 5+ projects within one year - Built and led a high-performing backend engineering team from scratch - Achieved measurable performance improvements (15% memory reduction) through technical optimization

Software Product Owner, Communication & Computing Dispatcher - Served as Product Owner for a cross-functional software team delivering a core communication and computing module within a central ECU project for an international automotive OEM. - Provided technical leadership in roadmap definition, sprint management, and coordination between base software and application-level components. - Collaborated with multiple stakeholder groups to align architecture decisions, improve configurability, and enhance overall software maintainability. - Spearheaded the development of a project-specific parameter handling solution that reduced the number of software build variants and simplified calibration and testing workflows. - Enabled more efficient release and validation cycles through the introduction of 30+ configurable calibration points, cutting development overhead and accelerating delivery. Key Achievements: - Reduced software build variants from multiple configurations to just two optimized versions - Introduced over 30 calibration points, significantly reducing release and testing effort - Improved cross-team collaboration and accelerated validation cycles

Team Lead – Hardware System Engineers - Led a team of 3–5 hardware system engineers responsible for the design and delivery of an automotive infotainment system for a German OEM. - Acted as the primary technical interface between Panasonic and the OEM, managing requirements, system concepts, and alignment across development and production teams. - Directed the sample delivery roadmap, ensuring alignment of specifications, milestones, and traceability documentation. - Conducted workflow audits across development and production sites to identify root causes of recurring delays. - Introduced a structured tracking mechanism that improved milestone visibility, clarified responsibilities, and ensured timely sample releases. Key Achievements: - Resolved recurring delivery delays by implementing a transparent and traceable release management process - Improved on-time delivery performance and strengthened customer confidence - Established a scalable project control framework later adopted in follow-up programs

Senior Research Engineer – Digital Design & Software Development (01/2015 – 12/2016) -Led two interdisciplinary teams (digital design and software development) of 7 engineers to deliver a full research prototype within a 6-month deadline - Researched and developed a heterogeneous many-core architecture with a compiler, OS, and runtime stack enabling parallel execution and resource allocation on accelerators, conceptually similar to modern CUDA-based programming models key Achievements: -Secured 4-year DFG research funding by preparing a successful grant proposal - Co-authored 2 peer-reviewed journals and 4 conference papers

Research Assistant – Digital Design & Software Development (05/2008 – 12/2014) - Conducted research on resource management in massively parallel accelerators for compute-intensive applications such as matrix operations, convolutions, graphics, and 3D workloads common in HPC and AI domains - Served as Teaching Assistant for Parallel Computing course, and led practical lab sessions on parallel programming, including excercises on CUDA and OpenMP key Achievements: - Co-authored 2 books, 4 peer-reviewed journals, and 14 conference papers, and delivered 10+ presentations at international conferences - Developed HW/SW co-design techniques for resource, power, and communication management in processor arrays, achieving up to 22% power savings and O(N) runtime complexity (at clock-system level), significantly outperforming SW-only approaches