Umur Darbaz

Leading architecture exploration and design efforts to improve scheduling performance and software productivity for the next generation of NVIDIA GPUs running cutting-edge deep learning workloads.

Workload characterization for containers, modeling novel CPU architectures for data centers. I was part of the FAST lab at UIUC. Advised by Nam Sung Kim and Josep Torrellas.

TA for Computer Architecture (ECE 411) and Embedded Systems (CS431) across 3 semesters. Guided over 300 students, instructed them on CPU microarchitecture, the RISC-V ISA, design tradeoffs, systems programming and multithreaded programming.

● Test-planned and brought up major features for embedded graphics processors. Developed new stimulus, checkers and coverage to verify the design. ● Enhanced verification flows to effectively test complex blocks. Collaborated with functional modeling and design teams to guide flow functionality. ● Drove debugging and triage efforts to bring RTL design in-line with micro-architectural specifications.

● Developed verification plans and enhanced testing environments to verify the RTL design of embedded graphics cores. Analyzed coverage points and targeted coverage holes in updates. ● Constructed automated and scalable verification flows and software infrastructure to efficiently test complex designs. The flows were reusable across different testbenches. ● Applied in-depth knowledge of microarchitecture, implementation and UVM to support development.

Computer Architecture, Parallel Programming and Systems. Advised by Nam Sung Kim and Josep Torrellas. Mentored by Dimitrios Skarlatos.