Umesh Patel

Umesh Patel

Founder and CEO @ Arastu Systems, Inc.

About

Seasoned Enthusiastic Executive with deep experience in driving product growth with innovative strategies for the various market. Contributed to many successful silicon valley startups in the field of semiconductor, embedded, software application systems from last 24 years where I engineered and managed products for better price and performance. Building and executing cohesive strategy across product engineering, sales, marketing and delivery, pursuing very aggressive growth targets year over year.

Country

United States

City

San Francisco Bay Area

Industry

Semiconductors

Skill

Requirements Analysis, Business Analysis, Verilog, TCL, PCIe, Perl, SPI, SATA, DDR, XAUI, ASIC, SoC, Logic Synthesis, Static Timing Analysis, FPGA, Semiconductors, Ethernet, I2C, RTL design, IC

Experience

Arastu Systems, Inc.

Founder and CEO

Arastu Systems, Inc.

LinkedIn
2014-8 - Present · 12 yrs 2 mos

San Francisco Bay Area

Arastu Systems is a passionate engineering company to provide Semiconductor and Software Engineering Services. We are in the business of Product Engineering Services for Hardware and Software. Our Software business has been in a unique position to provide comprehensive Digital Platform for IoT, where things, services and data come together to provide newer insight and experience. Get in touch with me at umesh@arastusystems.com We are working on very interesting projects. Indeed fun time. https://www.linkedin.com/company/arastu-systems

Infinera

Director

Infinera

LinkedIn
2021-9 - 2026-4 · 4 yrs 8 mos

Ahmedabad

Sibridge Technologies

Director, ASIC IP Solutions

Sibridge Technologies

LinkedIn
2012-1 - 2014-7 · 2 yrs 7 mos

I was responsible for IP Business. I was involved in day to day marketing and sales activity to manage expectation and effective ASIC business execution. Also, my team was involved in development and deployment of various complex interface IPs and ASIC SOC service projects. We managed to grow semiconductor IP revenue from almost zero to multi-million dollars. Sibridge VIP business was acquired by Cadence Design Systems.

PLX, an Avago Technologies Company

ASIC, Manager

PLX, an Avago Technologies Company

LinkedIn
2010-1 - 2012-1 · 2 yrs 1 mo

As a part Teranetics team, I managed various PHY projects and satellite communication semiconductor chips.

Glabs, Inc

Director

Glabs, Inc

2008-6 - 2010-1 · 1 yr 8 mos

San Francisco Bay Area

Founding member of ASIC/FPGA Lead Firm with Consultants Semiconductor SOC Architecture and Design for next generation multimedia chip. Managed many SoC project with complex peripherals like PCI express, 10G Ethernet, USB, SAS etc.

Teranetics

Principal

Teranetics

2005-1 - 2008-6 · 3 yrs 6 mos

San Francisco Bay Area

As one of the few member of Teranetics startup team to grow business from 10G Copper Ethernet PHY to Satellite communicate products. I was success part of semiconductor team to deliver multiple version of Chips in various processes from 130nm to 28nm Teranetics was acquired by PLX Technologies.

NetX

Design Engineer

NetX

LinkedIn
2002-4 - 2005-1 · 2 yrs 10 mos

San Francisco Bay Area

We were few to take Ethernet TCP/IP communication in hardware to next level. I was responsible of various part of peripherals design and verification of multi-million gates ASIC. Netgen was acquired by Qlogic.

Vitesse Semiconductor is now Microsemi

Staff Design Engineer

Vitesse Semiconductor is now Microsemi

LinkedIn
1998-5 - 2002-3 · 3 yrs 11 mos

San Francisco Bay Area

I was part of Startup XaQti as a Front End Design Verification Engineer. We were making ethernet termination ToE engine for 10G link. XaQti was acquired by Vitesse Semiconductor

Synopsys Inc

Design Application Engineer

Synopsys Inc

LinkedIn
1996-6 - 1998-5 · 2 yrs

San Francisco Bay Area

Interacted with the customer base to provide advanced technical consulting knowledge, like to develop methodology for ASICs and FPGAs according to the customer’s applications. Expert Consultant for Design Compiler, Test Compiler, FPGA Compiler / Express, Primetime, Library Compiler, Floorplan Manager, VHDL(HDL) compiler Synopsys Tools.

Education

California State University, Northridge

California State University, Northridge

LinkedIn

Computer Engineering

1994 - 1996 · 2 yrs
The Maharaja Sayajirao University of Baroda

The Maharaja Sayajirao University of Baroda

LinkedIn

EE

1988 - 1992 · 4 yrs

Umesh Patel's Contact Information

Email

******@***.com

Phone

(**) *** ****

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