UDAY MAURYA
Senior Engineer - RFIC Design @ Axiro Semiconductor
About
I am an RF and mm-wave integrated circuit (IC) designer specializing in CMOS radios. I work primarily in 65 nm CMOS technology and have experience across the full design cycle from architecture definition and circuit-level design to EM simulation, layout, tape-out, and measurement. Over the past few years, I have successfully taped out two ICs at mm-wave frequencies, demonstrating expertise in both active and passive RF/mm-wave design: ✅Tapeouts: ✨Chip1 (2023, TSMC 65nm GP)- Developed a low-loss 5G mmWave Transmit/Receive front-end module in 65 nm bulk CMOS for the FR2 n260 band (37–40 GHz). ✨Chip2 (2024, TSMC 65nm GP)- Developed a mm-Wave Bidirectional transceiver with baseband phase shifting in 65 nm bulk CMOS for the 5G phased array application. ⭐** *Key Skillsets ***⭐ ⭐**EDA Tools and Softwares: Proficient in Cadence (Virtuoso, Spectre, EMX-Integrand, Assura), Mentor Graphics (Calibre), ngspice, LTspice, and Eagle PCB. ⭐**Measurements and Characterization: -- Skilled in on-wafer DC/RF probing, On-wafer S-parameter, load-pull, Noise figure and EVM measurements, de-embedding, debugging. --Skilled in operating VNA, DC/RF probe stations, DSO, Vector Spectrum Analyzers, Function Generators, Analog Signal generators, Vector Signal Generators. ⭐**Core Competencies --Active Circuit Design: Power Amplifiers, LNAs, Oscillators, Mixers, Frequency Multipliers, Phase Shifters. --Passive RF Design: Transformers, Inductors, Coupled-line Couplers, Baluns, Power Dividers/Combiners, Poly phase filters, Quadrature Hybrids Couplers
India
North Guwahati
Semiconductors
Tape out, Radio Frequency (RF), Integrand, EMX, Calbre, Cadence Virtuoso, Cadence Spectre, Cadence Virtuoso Layout Editor, full custom design, semicustom design, Field-Programmable Gate Arrays (FPGA), Synopsys tools, Eagle PCB, Proteus, xillinx , Xilinx ISE, LTSpice, hspice, TINA, Microsoft Office
Experience
Education
UDAY MAURYA's Contact Information
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