Todd Tah-te Shih

Senior Technical Manager @ TSMC

About

Extensive hands-on experience in a wide range of product types ranging from semiconductor chips production to Fab engineering & Quality management. Experienced in technical team leadership and project management. Strong background in process development for advanced memory & logic device. And, well-versed in all aspects of device manufacturing, including material properties, semiconductor processes, materials, tests, design, and customer satisfaction。 Competence: 1. Strong skills to deliver patterning process (Litho/ETCH). Also, knowledge of design for manufacturing (DFM) during development stage. 2.Quality & reliability background to offer well planned FAB start up , tool selection , schedule control, ramping up plan, automation(CIM) and inline control plan(SPC/FDC). 3. engineering team coaching with KT method & DOE problem solving skills in supporting process developing , fast production and yield driven.

Country

Taiwan

City

Taichung City

Industry

Electrical & Electronic Manufacturing

Skill

Project Management, Supply Chain Management, Product Quality, Engineering, opc, OPC, Certified Quality Engineer (CQE), DRAM(Trench & Stack), Statistical Process Control (SPC), Robust Process Engineering, Taguchi Methods, ASML Immersion Scanner, Quality Engineerng , Reliability Engineering, Immersion Lithography, Mask technology, Resist & Material , OCD & CDSEM Metrology, KT method, Design of Experiments (DOE)

Experience

Senior Technical Manager

TSMC

2026-2 - Present · 8 mos

Metrology Dept Manger

TSMC

2021-12 - 2026-2 · 4 yrs 3 mos

Taichung City, Taiwan

- 7nm/6nm Metrology Process Quality & Manufacturing - Optical CD LIB tunning & development for Etch 3D profile (FinFET) - Film thickness measurement using optical ellipsometer (DIF,CVD.PVD,CMP) - Stress & Resistivity measurement by optical prober CVDPVD) - CD SEM measurement for PHOTO, ETCH & EPI - Defect pattern inspection tool bright field & dark field

Litho Module Dept Engineering Manager

TSMC

2011-4 - 2021-12 · 10 yrs 9 mos

Taichung,Taiwan

28nm,22nm,10nm,7nm,6nm Logic process manufacturing and yield improvement 300mm Photo Dept. Manager (Mar 2011 ~ 2022) TSMC Semiconductor, Tai-Chung, Taiwan - 10nm/7nm/6nm Logic Process Quality & Manufacturing - 28nm/22nm Logic Process Quality & Manufacturing - Litho/Etch process CDU window & profile compensation - OPC optimization for 248 to 193 layer & Immersion 0.22um Metal converasion - Litho mask inspection and tool qualification - FDC/R2R/Data Mining/Digital FAB Automation by AI - SPC process Control, Yield Improvement, Cycle time reduction，COST reduction. Productivity enhancement & People effective improvement

Metrology Department Manager

台積電 JASM

2024-2 - Present · 2 yrs 8 mos

Japan

Litho Module Manager

Inotera

2007-12 - 2011-4 · 3 yrs 5 mos

台灣 New Taipei City 林口區

3xnm,4xnm,6xnm,7xnm DRAM Process Engineering for Litho & Etch. Process Transfer , set up and yield ramping - 70nm/45nm DRAM process transfer, characterization, qualification, ramp up for 126K/mo - Material Cost reduction and productivity enhancement. - Spec to Yield correlation based on OVL& alignment strategy

Photo Dept manager

Winbond

2004-4 - 2007-11 · 3 yrs 8 mos

Taichung Taiwan

- 110nm/90nm/80nm DRAM Technology transfer from Infineon. Process set up, release, & ramp-up to 24K - 1st 12 in FAB startup. Assignment 12moths in Dresden, Germany. Infineon 12 in Fab. acting as module leader. - Scanner OPC matching test reticle design using SCD & simulation with ASML Litho Cruiser. - ASML Litho guide platform to monitor Pupil shape, SAMO, ILIAS, Dose DSP Test - APC-FDC Platform for Data Mining & Virtual Metrology purpose. - Alignment Strategy Optimization with Alignment Advisor. - Lens Heating Correction ASCAL set up on all L/S layers.

Sr. Mask process engineer

Photronics

2002-2 - 2004-3 · 2 yrs 2 mos

Austin, Texas Area

- 90nm,110nm node DRAM/Flash eAPSM development and manufacturing. - 50Kev Toshiba EB3500B E-Beam group leader and 110 nm node mask making Integration engineer, specialize in memory ,logic or embedded type of product. - Electron Proximity effect (PEC) and Back Scattering electron fogging effect (GDC) characterization

資深工程師

NXP acquires Freescale Semiconductor

2000 - 2002 · 2 yrs

美國

- 0.18um & 0.25um (Cu-line) Logic/SRAM Photo process owner, SPC control, Gate CD control, and yield enhancement - 0.18um (Cu-line) SOI Photo process transfer from APRDL and pilot process set up at MOS13. - Photo Advanced Process Control software (Dose/Overlay) co-development and implementation.

Senior Engineer

TSMC Washington

1998 - 2000 · 2 yrs

- 0.18um Low Voltage SRAM development - 0.18um 6T High Speed SRAM development - 0.25/0.22um Logic process Photo module transfer and set up.

工程師

Vanguard International Semiconductor Corporation (VIS)

1994-4 - 1998-2 · 3 yrs 11 mos

Hsinchu City, Taiwan, Taiwan

Photo Module Engineer - 0.33/0.37/0.4um 16MDRAM production process development and ramp-up - 0.4um 16MDRAM photo process project coordinator. - Responsible for monthly output from 12k/mo. to 15k/mo. for 8” wafers.