Rajamani Sethuram
Custom CPU DFT @ Qualcomm
About
Back at grad school, when I defended my dissertation on test cost reduction and test quality improvements little did I knew the scope and impact of DFT on the overall chip design and productization cycle. Looking back on the 15+ years of implementing and leading DFT for socs ranging from cellphones, datacenter, AI, and automotive chips, I can vouch that innovation in DFT is super critical to the success of silicon - from design quality to product time-to-market, it affects everything. Juxtaposed between design and silicon engineering team, I have driven successful tapeouts, silicon bringup, and enabled product and test engineering teams for a smooth ramp-up to production. I have many years of experience developing EDA tools and methodologies, DFT architecture and implementation that resulted multiple patents and several publications. I have lead global teams implementing DFT for very large SoCs. My tenets for leading team are: a) direct and effectively communicate risks, dependencies, and critical DFT metrics, b) lead with energy, passion and curiosity to help bring the best out of engineers, and c) aspire, innovate, and never settle for less to deliver best-in-class DFT solution at the speed of light!
United States
San Jose
Computer Hardware
EDA, Cadence Virtuoso, Perl, Primetime, Static Timing Analysis, Shell Scripting, ATPG, Vera, RTL verification, Digital Electronics, Testing, SystemVerilog, ASIC, Verilog, TCL
Experience

Principal Engineer
Santa Clara, California
At Nvidia, I had the privilege to lead a world-class global team of DFT engineers delivering state-of-the-art DFT solution for automotive, gaming, and industrial automation chips (https://bit.ly/3nOKrwi). Extremely proud to have been part of the team that is changing the future of autonomous vehicle industry (watch https://bit.ly/3ABt1ee)

Teaching Assistant Professor
North Carolina State University
Raleigh-Durham, North Carolina Area
Digital Logic Design at the ECE dept. of NCSU

Research Assistant
NEC Research Labs
Research related to Test cost reduction for Structured ASICs and regular cell-based ASICs
Rajamani Sethuram's Contact Information
Phone
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